Altera Hybrid Memory Cube Controller - Manual (Page 31)

Interface to External I 2 C Master
The HMC Controller IP core requires that you instantiate an external I 2 C master module in your design.
This external I 2 C master module must coordinate link initialization on the link between the HMC and the
HMC Controller. The I 2 C master coordinates with the HMC Controller internal initialization state
machine and programs configuration registers in the HMC device to which your IP core connects.
Separating the HMC Controller IP core from the I
2 C master module provides design flexibility. Because
the IP core does not include the I 2 C master module, you can instantiate a single I 2 C master to control link
initialization for multiple HMC Controller IP cores. A single I 2 C master module can also control other
I 2 C slaves.
Related Information
• Adding the External I2C Master Module on page 2-15
Information about how to connect the HMC Controller IP core to the external I2C master module.
• Signals on the Interface to the I2C Master on page 4-9
Describes the signals on this interface and the four-way handshaking protocol that the HMC
Controller IP core implements and that the I 2 C master must implement for correct IP core function‐
ality.
Control and Status Register Interface
The control and status register interface provides access to the HMC Controller IP core internal control
and status registers. This interface does not provide access to the transceiver registers.
The control and status interface complies with the Avalon Memory-Mapped (Avalon-MM) specification
defined in the Avalon Interface Specifications.
The control and status interface provides a 32-bit wide data bus for register content. All HMC Controller
control and status registers are 32 bits wide and all register accesses through the control and status
interface read or write the full 32 bits of register content.
Related Information
• Control and Status Interface Signals on page 4-10
• HMC Controller IP Core Register Map on page 5-1
• Avalon Interface Specifications
Status and Debug Interface
The status and debug interface provides signals to communicate successful link initalization and to
support debugging of your HMC system.
Related Information
Status and Debug Signals on page 4-11
Transceiver Control Interfaces
The HMC Controller IP core supports the following transceiver control interfaces:
External PLL Interface on page 3-4
Transceiver Reconfiguration Interface on page 3-4
UG-01152
2015.05.04
Interface to External I 2 C Master 3-3
Functional Description Altera Corporation
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