Altera Hybrid Memory Cube Controller - Manual (Page 65)

Figure 6-1: High Level Block Diagram for the HMC Controller IP Core Example Design
The example design configures a single ATX PLL in xN bonding mode and connects it to the HMC
Controller IP core.
HMC Controller IP Core
TX
FIFO
TX
MAC
RX
MAC
Control and
Status Interface
Initialization Initialization
State Machine State Machine
Arria 10
Transceiver
Reconfiguration
Interface
Avalon-MM
TX Lane
Swapper
RX Lane
Swapper
Avalon-MM
I C Master
Transceiver
x16
Data Path
Request
Generator
and
Response
Monitor
Test
Controller
TX PLLs
HMC Device
LEDs
Arria 10 Device
Board
2
Clocks & Reset
The example design is provided as a Quartus II project. The example design targets the
10AX115S3F45I2SGES Arria 10 device in an Arria 10 GX FPGA Development Kit, with an HMC
mezannine card connected through the FMC connectors. To use a different device or development kit,
you must modify the project.
To set up, compile the example design, configure the example design on the device, and run the hardware
testbench on the design, follow these steps:
1. In the Quartus II software IP Catalog, under Memory Interfaces and Controllers, select Hybrid
Memory Cube Controller and click Add.
2. When prompted you must specify the IP core instance name. If you specify the name <my_ip>, the
software generates the file <my_ip> .qsys .
3. When prompted you must specify the Arria 10 device name. The example design is tested with the
10AX115S3F45I2SGES device and compiles correctly for all Arria 10 devices with the same size,
configuration, and pinout.
4. In the HMC Controller parameter editor, set the parameter values to configure your IP core variation.
5. Click the Example Design button and specify the desired location of the example design. The Quartus
II software creates an example design that includes a copy of the HMC Controller IP core.
6. Optionally, click Finish and then Yes or No to close the HMC Controller parameter editor.
7. Click File > Open Project.
6-2 HMC Controller IP Core Example Design
UG-01152
2015.05.04
Altera Corporation HMC Controller IP Core Example Design
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