Altera Hybrid Memory Cube Controller - Manual (Page 60)

Bits Field Name Type Value on
Reset
Description
14
Response Queue
ECC Error
Enable
RW 0x0 Enables
Response Queue ECC Error
interrupt.
13
FERR_N Enable
RW 0x0 Enables
FERR_N
interrupt.
12
Retry Buffer
Uncorrectable
ECC Error
Enable
RW 0x0 Enables
Retry Buffer Uncorrectable ECC Error
interrupt.
11
Retry Buffer
ECC Error
Enable
RW 0x0 Enables
Retry Buffer ECC Error
interrupt.
10 Reserved RO 0x0
9
No More Tokens
Enable
RW 0x0 Enables
No More Tokens
interrupt.
8
Retry Buffer
Full Enable
RW 0x0 Enables
Retry Buffer Full
interrupt.
7 Reserved RO 0x0
6
RX Error
Response
Overflow
Enable
RW 0x0 Enables
RX Error Response Overflow
interrupt.
5
RX Error
Response
Enable
RW 0x0 Enables
RX Error Response
interrupt.
4
Fatal Error
Enable
RW 0x0 Enables
Fatal Error
interrupt.
3
Remote Error
Enable
RW 0x0 Enables
Remote Error
interrupt.
2
SEQ Error
Enable
RW 0x0 Enables
SEQ Error
interrupt.
1
LNG/DLN Error
Enable
RW 0x0 Enables
LNG/DLN Error
interrupt.
0
CRC Error
Enable
RW 0x0 Enables
CRC Error
interrupt.
Table 5-10: HMC Controller IP Core GLOBAL_INTERRUPT_ENABLE Register at Offset 0x28
Gates the
INTERRUPT_ENABLE
register.
Bits Field Name Type Value on
Reset
Description
31:1 Reserved RO 0x00000000
5-8 Interrupt Related Registers
UG-01152
2015.05.04
Altera Corporation HMC Controller IP Core Register Map
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