Altera Hybrid Memory Cube Controller User Manual

Page 43

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Signal Name

Direction

Description

dp_rsp_size[2:0]

Output

Indicates the size of the payload associated with this

response. If the current response is a Read response,

indicates the size of the payload in

dp_rsp_data

.

During a response with an associated payload, the IP core

sets this signal to one of the following valid values:
• 3'b000 indicates a 16-byte payload or a Write response.

• 3'b001 indicates a 32-byte payload.

• 3'b010 indicates a 48-byte payload (half-width IP cores

only).

• 3'b011 indicates a 64-byte payload.

• 3'b100 indicates a 80-byte payload (half-width IP cores

only).

• 3'b101 indicates a 96-byte payload (half-width IP cores

only).

• 3'b110 indicates a 112-byte payload (half-width IP

cores only).

• 3'b111 indicates a 128-byte payload.
During a response with no associated payload, the value of

this signal is undefined. Responses with no associated

payload are the responses for which

dp_rsp_cmd[0]

has

the value of 1.
The IP core maintains the value of this signal for the

duration of a multi-cycle read data transfer.

dp_rsp_data[511:0]

(for full-

width IP cores)

dp_rsp_data[255:0]

(for half-

width IP cores)

Output

Read response data.
During a response with no associated payload, the value of

this signal is undefined. Responses with no associated

payload are the responses for which

dp_rsp_cmd[0]

has

the value of 1.
If the size of the payload is not an integer multiple of the

data bus width, then in the final data transfer cycle, the IP

core transfers the remaining read payload in the least

significant bytes of

dp_rsp_data

. For example, the IP

core:
• Transfers a 16-byte payload in

dp_rsp_data[127:0]

.

• Transfers a 32-byte payload (from a full-width or half-

width IP core) in

dp_rsp_data[255:0]

.

• Transfers the final (most significant) 16 bytes of a 112-

byte payload from a half-width IP core in

dp_rsp_

data[127:0]

in the fourth data transfer clock cycle.

4-6

Application Response Interface

UG-01152

2015.05.04

Altera Corporation

HMC Controller IP Core Signals

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