Altera Hybrid Memory Cube Controller - Manual (Page 3)

HMC Controller IP Core Signals........................................................................ 4-1
Application Interface Signals......................................................................................................................4-1
Application Request Interface........................................................................................................4-1
Application Response Interface..................................................................................................... 4-4
HMC Controller IP Core Data Path Example............................................................................. 4-7
HMC Interface Signals................................................................................................................................ 4-8
Signals on the Interface to the I 2 C Master................................................................................................4-9
Control and Status Interface Signals....................................................................................................... 4-10
Status and Debug Signals..........................................................................................................................4-11
Clock and Reset Signals.............................................................................................................................4-12
Transceiver Reconfiguration Signals.......................................................................................................4-13
Signals on the Interface to the External PLLs........................................................................................ 4-15
HMC Controller IP Core Register Map..............................................................5-1
CONTROL Register.....................................................................................................................................5-2
XCVR_STATUS Register............................................................................................................................5-3
LANE_STATUS Register............................................................................................................................5-3
LINK_STATUS Register.............................................................................................................................5-4
ERROR_RESPONSE Register.................................................................................................................... 5-5
Interrupt Related Registers.........................................................................................................................5-5
Error and Retry Statistics Registers........................................................................................................... 5-9
HMC Controller IP Core Example Design......................................................... 6-1
Additional Information......................................................................................A-1
HMC Controller IP Core User Guide Revision History....................................................................... A-1
How to Contact Altera............................................................................................................................... A-1
Typographic Conventions......................................................................................................................... A-2
About the Altera Hybrid Memory Cube Controller IP Core TOC-3
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