Altera Hybrid Memory Cube Controller - Manual (Page 27)

Understanding the Testbench
Altera provides an example design with the HMC Controller IP core. The example design is available both
for simulation of your IP core and for compilation. The example design in simulation functions as the
HMC Controller IP core testbench.
If you click Example Design in the HMC Controller parameter editor, the Quartus II software generates a
demonstration testbench. The parameter editor prompts you for the desired location of the testbench.
To simulate the testbench, you must provide your own HMC bus functional model (BFM). The example
design simulates with the Micron Hybrid Memory Cube BFM. The testbench does not include an I 2 C
master module, because the Micron HMC BFM does not support configuration by an I 2 C module.
In simulation, the testbench controls a TX PLL and the data path interfaces to perform the following
sequence of actions:
1. Configures the HMC BFM with the HMC Controller IP core data rate and channel width, in Response
Open Loop Mode.
2. Establishes the link between the BFM and the IP core.
3. Directs the IP core to write four packets of data to the BFM.
4. Directs the IP core to read back the data from the BFM.
5. Checks that the read data matches the write data.
6. If the data matches, displays
TEST_PASSED
.
Related Information
HMC Controller IP Core Example Design on page 6-1
The HMC Controller IP core example design provides a testbench for simulation. The example design
also supports compilation and configuration.
Generating and Running the Testbench
To simulate the testbench, you must provide your own HMC bus functional model (BFM). The testbench
is designed for use with the HMC BFM r27742.
To generate and simulate the HMC Controller IP core example design, follow these steps:
1. In the Quartus II software IP Catalog, select the HMC Controller IP core and click Add.
2. When prompted you must specify the IP core instance name. If you specify the name <my_ip>, the
software generates the file <my_ip> .qsys .
3. In the HMC Controller parameter editor, set the parameter values to configure the IP core variation
you wish to simulate.
4. Click the Example Design button and specify the desired location of the testbench.
5. On the command line, change directory to <example design directory> /example_design/sim .
6. Create the simulation scripts by typing
make scripts
. The scripts are designed and tested for use with
the HMC BFM r27742.
Note: You can type
make clean
to delete all simulation-generated files.
make clean
does not delete
the scripts that the
make scripts
command creates.
7. Execute the simulation script in the directory by typing the relevant command line.
2-18 Understanding the Testbench
UG-01152
2015.05.04
Altera Corporation Getting Started with the HMC Controller IP Core
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