Hmc controller ip core register map, Hmc controller ip core register map -1 – Altera Hybrid Memory Cube Controller User Manual
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HMC Controller IP Core Register Map
5
2015.05.04
UG-01152
The HMC Controller IP core internal registers are 32 bits wide and are accessible to you using the control
and status interface, an Avalon-MM interface which conforms to the Avalon Interface Specifications.
All of these registers are 32 bits wide and the addresses are shown as hexadecimal values. The registers can
be accessed only on a 32-bit (4-byte) basis. The addressing for the registers therefore increments by units
of 4.
Write accesses to a Reserved or undefined location have no effect. Read accesses to a Reserved or
undefined location return an undefined result.
Table 5-1: Register Access Codes
Lists the access codes used to describe the type of register bits.
Code
Description
RW
Read / write
RO
Read only
RW1C
Read / write 1 to clear
RTC
Read to clear
Table 5-2: Control and Status Register Map
Offset
Register Name
Location of Additional Information
0x00
Reserved
0x04
CONTROL
0x08
XCVR_STATUS
0x0C
LANE_STATUS
0x10
LINK_STATUS
0x14
ERROR_RESPONSE_CAPTURE
0x18, 0x1C Reserved
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