Altera Cyclone V GX FPGA Development Board - Manual (Page 11)

Chapter 2: Board Components 2–3
Board Overview
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
SW3 Board settings DIP switch
Controls the MAX V CPLD 5M2210 System Controller functions such
as clock enable, SMA clock input control, and which image to load
from flash memory at power-up.
SW4 PCI Express DIP switch
Controls the PCI Express lane width by connecting the prsnt pins
together on the PCI Express edge connector.
S7 Program select push button
Toggles the program select LEDs, which selects the program image
that loads from flash memory to the FPGA.
S6
Program configuration push
button Load image from flash memory to the FGPA based on the settings of
the program select LEDs.
D15 Configuration done LED Illuminates when the FPGA is configured.
D17 Load LED
Illuminates when the MAX V CPLD 5M2210 System Controller is
actively configuring the FPGA.
D16 Error LED Illuminates when the FPGA configuration from flash memory fails.
D23 Power LED Illuminates when 5.0-V power is present.
D12, D13, D14 Program select LEDs
Illuminates to show the LED sequence that determines which flash
memory image loads to the FPGA when you press the program select
push button. Refer to
Table 2–6 for the LED settings.
D19, D20, D21,
D22, D24
Ethernet LEDs
Illuminates to show the connection speed as well as transmit or
receive activity.
D1, D2 HSMC port LEDs You can configure these LEDs to indicate transmit or receive activity.
D3 HSMC port present LED Illuminates when a daughtercard is plugged into the HSMC port A.
D8, D9, D10 PCI Express link LEDs
You can configure these LEDs to indicate the PCI Express link width
(x1, x4) and Gen1 link.
Clock Circuitry
U25 Quad-output oscillator
Programmable oscillator with default frequencies of 125 MHz,
409.6 MHz, 156.25 MHz, and 100 MHz. The frequency is
programmable using the clock control GUI running on the MAX V
CPLD 5M2210 System Controller.
X2 148.5-MHz oscillator
148.500-MHz voltage controlled crystal oscillator for the serial digital
interface (SDI) video. This oscillator is programmable to any frequency
between 20–810 MHz using the clock control GUI running on the
MAX V CPLD 5M2210 System Controller.
X4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.
X1 100-MHz oscillator
100.000-MHz crystal oscillator for the MAX V CPLD 5M2210 System
Controller.
J2, J3, J6, J7 Transceiver SMA connectors Drives serial data input/output to or from the SDI video port.
J16, J17 Clock input SMA connectors
Drive LVPECL-compatible clock inputs into the clock multiplexer
buffer.
J4 Clock output SMA connector Drive out 2.5-V CMOS clock output from the FPGA.
General User Input/Output
D4–D7 User LEDs Four user LEDs. Illuminates when driven low.
SW2 User DIP switch Quad user DIP switches. When the switch is ON, a logic 0 is selected.
S2 CPU reset push button Reset the FPGA logic.
Table 2–1. Board Components (Part 2 of 3)
Board Reference Type Description