Altera Cyclone V GX FPGA Development Board User Manual
Page 17
Chapter 2: Board Components
2–9
MAX V CPLD 5M2210 System Controller
May 2013
Altera Corporation
Cyclone V GX FPGA Development Board
Reference Manual
N2
FSM_D12
2.5-V
FSM data bus
L3
FSM_D13
2.5-V
FSM data bus
R1
FSM_D14
2.5-V
FSM data bus
P2
FSM_D15
2.5-V
FSM data bus
L15
HSMA_PRSNTN
2.5-V
HSMC port A present
L6
JTAG_5M2210_TDI
2.5-V
MAX V CPLD JTAG chain data in
M5
JTAG_5M2210_TDO
2.5-V
MAX V CPLD JTAG chain data out
P3
JTAG_TCK
2.5-V
JTAG chain clock
P11
M570_CLOCK
2.5-V
25-MHz clock to embedded USB-Blaster II for sending
FACTORY command
P12
M570_PCIE_JTAG_EN
2.5-V
Low signal to disable the embedded USB-Blaster II when PCI
Express is the master to the JTAG chain
B10
MAX5_BEN0
2.5-V
FSM bus MAX V byte enable 0
A9
MAX5_BEN1
2.5-V
FSM bus MAX V byte enable 1
C11
MAX5_BEN2
2.5-V
FSM bus MAX V byte enable 2
C10
MAX5_BEN3
2.5-V
FSM bus MAX V byte enable 3
P8
MAX5_CLK
2.5-V
FSM bus MAX V clock
B12
MAX5_CSN
2.5-V
FSM bus MAX V chip select
C12
MAX5_OEN
2.5-V
FSM bus MAX V output enable
A10
MAX5_WEN
2.5-V
FSM bus MAX V write enable
L13
MAX_CONF_DONEN
2.5-V
Embedded USB-Blaster II configuration done LED
P14
MAX_ERROR
2.5-V
FPGA configuration error LED
D14
MAX_LOAD
2.5-V
FPGA configuration active LED
M9
MAX_RESETN
2.5-V
MAX V reset push button
F11
MSEL0
2.5-V
FPGA mode select 0
F12
MSEL1
2.5-V
FPGA mode select 1
K12
MSEL2
2.5-V
FPGA mode select 2
M14
MSEL3
2.5-V
FPGA mode select 3
N13
MSEL4
2.5-V
FPGA mode select 4
J15
OVERTEMP
2.5-V
Temperature monitor fan enable
M7
PCIE_JTAG_EN
2.5-V
DIP switch to enable the PCI Express JTAG master
L12
PGM_CONFIG
2.5-V
Load the flash memory image identified by the PGM LEDs
M4
PGM_LED0
2.5-V
Flash memory PGM select indicator 0
K13
PGM_LED1
2.5-V
Flash memory PGM select indicator 1
L11
PGM_LED2
2.5-V
Flash memory PGM select indicator 2
L4
PGM_SEL
2.5-V
Toggles the PGM_LED[2:0] LED sequence
K14
SDI_FAULT
2.5-V
SDI data transmission fault
N5
SDI_RX_BYPASS
2.5-V
SDI equalization bypass
P6
SDI_RX_EN
2.5-V
SDI receive enable
Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 4 of 5)
Board
Reference (U12)
Schematic Signal Name
I/O Standard
Description