Altera Cyclone V GX FPGA Development Board - Manual (Page 46)

2–38 Chapter 2: Board Components
Memory
Cyclone V GX FPGA Development Board May 2013 Altera Corporation
Reference Manual
Table 2–29 lists the DDR3B pin assignments, signal names, and functions. The signal
names and types are relative to the Cyclone V GX in terms of I/O setting and
direction.
Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board Reference
Schematic
Signal Name
Cyclone V GX
Pin Number
I/O Standard Description
DDR3 x16 (U6)
N3 DDR3B_A0 Y30 1.5-V SSTL Class I Address bus
P7 DDR3B_A1 R28 1.5-V SSTL Class I Address bus
P3 DDR3B_A2 AA29 1.5-V SSTL Class I Address bus
N2 DDR3B_A3 W29 1.5-V SSTL Class I Address bus
P8 DDR3B_A4 U23 1.5-V SSTL Class I Address bus
P2 DDR3B_A5 AA30 1.5-V SSTL Class I Address bus
R8 DDR3B_A6 R23 1.5-V SSTL Class I Address bus
R2 DDR3B_A7 AC30 1.5-V SSTL Class I Address bus
T8 DDR3B_A8 T23 1.5-V SSTL Class I Address bus
R3 DDR3B_A9 AB29 1.5-V SSTL Class I Address bus
L7 DDR3B_A10 R30 1.5-V SSTL Class I Address bus
R7 DDR3B_A11 R26 1.5-V SSTL Class I Address bus
N7 DDR3B_A12 T25 1.5-V SSTL Class I Address bus
T3 DDR3B_A13 AD29 1.5-V SSTL Class I Address bus
M2 DDR3B_BA0 W30 1.5-V SSTL Class I Bank address bus
N8 DDR3B_BA1 T24 1.5-V SSTL Class I Bank address bus
M3 DDR3B_BA2 V30 1.5-V SSTL Class I Bank address bus
K3 DDR3B_CASN T30 1.5-V SSTL Class I Row address select
K9 DDR3B_CKE L28 1.5-V SSTL Class I Column address select
J7 DDR3B_CLK_P P22
Differential 1.5-V SSTL
Class I
Differential output clock
K7 DDR3B_CLK_N P23
Differential 1.5-V SSTL
Class I
Differential output clock
L2 DDR3B_CSN U29 1.5-V SSTL Class I Chip select
E7 DDR3B_DM0 C29 1.5-V SSTL Class I Write mask byte lane
D3 DDR3B_DM1 D29 1.5-V SSTL Class I Write mask byte lane
E3 DDR3B_DQ0 D30 1.5-V SSTL Class I Data bus byte lane 0
F7 DDR3B_DQ1 C30 1.5-V SSTL Class I Data bus byte lane 0
F2 DDR3B_DQ2 F29 1.5-V SSTL Class I Data bus byte lane 0
F8 DDR3B_DQ3 K22 1.5-V SSTL Class I Data bus byte lane 0
H3 DDR3B_DQ4 E28 1.5-V SSTL Class I Data bus byte lane 0
H8 DDR3B_DQ5 K21 1.5-V SSTL Class I Data bus byte lane 0
G2 DDR3B_DQ6 G29 1.5-V SSTL Class I Data bus byte lane 0
H7 DDR3B_DQ7 L23 1.5-V SSTL Class I Data bus byte lane 0
D7 DDR3B_DQ8 J23 1.5-V SSTL Class I Data bus byte lane 1