Altera Cyclone V GX FPGA Development Board - Manual (Page 44)

2–36 Chapter 2: Board Components
Memory
Cyclone V GX FPGA Development Board May 2013 Altera Corporation
Reference Manual
K9 DDR3A_CKE AK18 1.5-V SSTL Class I Column address select
K7 DDR3A_CLK_P Y13 1.5-V SSTL Class I Differential output clock
J7 DDR3A_CLK_N AA14 1.5-V SSTL Class I Differential output clock
L2 DDR3A_CSN Y12 1.5-V SSTL Class I Chip select
E7 DDR3A_DM2 AJ23 1.5-V SSTL Class I Write mask byte lane
D3 DDR3A_DM3 AJ27 1.5-V SSTL Class I Write mask byte lane
F2 DDR3A_DQ16 AE18 1.5-V SSTL Class I Data bus byte lane 2
F8 DDR3A_DQ17 AD18 1.5-V SSTL Class I Data bus byte lane 2
E3 DDR3A_DQ18 AJ20 1.5-V SSTL Class I Data bus byte lane 2
F7 DDR3A_DQ19 AK22 1.5-V SSTL Class I Data bus byte lane 2
H3 DDR3A_DQ20 AF19 1.5-V SSTL Class I Data bus byte lane 2
G2 DDR3A_DQ21 AF18 1.5-V SSTL Class I Data bus byte lane 2
H7 DDR3A_DQ22 AH21 1.5-V SSTL Class I Data bus byte lane 2
H8 DDR3A_DQ23 AK23 1.5-V SSTL Class I Data bus byte lane 2
A2 DDR3A_DQ24 AG19 1.5-V SSTL Class I Data bus byte lane 3
C2 DDR3A_DQ25 AG18 1.5-V SSTL Class I Data bus byte lane 3
D7 DDR3A_DQ26 AH24 1.5-V SSTL Class I Data bus byte lane 3
A7 DDR3A_DQ27 AK25 1.5-V SSTL Class I Data bus byte lane 3
A3 DDR3A_DQ28 AE20 1.5-V SSTL Class I Data bus byte lane 3
C3 DDR3A_DQ29 AD19 1.5-V SSTL Class I Data bus byte lane 3
B8 DDR3A_DQ30 AG24 1.5-V SSTL Class I Data bus byte lane 3
C8 DDR3A_DQ31 AK26 1.5-V SSTL Class I Data bus byte lane 3
F3 DDR3A_DQS_P2 Y20
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 2
G3 DDR3A_DQS_N2 AA20
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 2
C7 DDR3A_DQS_P3 AB19
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 3
B7 DDR3A_DQS_N3 AC19
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 3
K1 DDR3A_ODT AH14 1.5-V SSTL Class I On-die termination enable
J3 DDR3A_RASN AG9 1.5-V SSTL Class I Row address select
T2 DDR3A_RESETN AK21 1.5-V SSTL Class I Reset
L3 DDR3A_WEN AK5 1.5-V SSTL Class I Write enable
L8 DDR3A_ZQ2 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3 x8 (U23)
K3 DDR3A_A0 AJ12 1.5-V SSTL Class I Address bus
L7 DDR3A_A1 AK12 1.5-V SSTL Class I Address bus
L3 DDR3A_A2 AH11 1.5-V SSTL Class I Address bus
Table 2–29. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board Reference
Schematic
Signal Name
Cyclone V GX
Pin Number
I/O Standard Description