Altera Cyclone V GX FPGA Development Board - Manual (Page 51)

Chapter 2: Board Components 2–43
Memory
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
Flash
The development board supports a 512-MB CFI-compatible synchronous flash device
for non-volatile storage of FPGA configuration data, board information, test
application data, and user code space. This device is part of the shared FSM bus that
connects to the flash memory, SSRAM, and MAX V CPLD 5M2210 System Controller.
This 16-bit data memory interface can sustain burst read operations at up to 52 MHz
for a throughput of 832 Mbps per device. The write performance is 270 µs for a single
word buffer while the erase time is 800 ms for a 128 K array block.
Table 2–32 lists the flash pin assignments, signal names, and functions. The signal
names and types are relative to the Cyclone V GX in terms of I/O setting and
direction.
72 FSM_D6 A8 2.5-V Data bus
73 FSM_D7 B7 2.5-V Data bus
23 FSM_D8 B8 2.5-V Data bus
22 FSM_D9 C9 2.5-V Data bus
19 FSM_D10 A9 2.5-V Data bus
18 FSM_D11 A10 2.5-V Data bus
12 FSM_D12 C10 2.5-V Data bus
13 FSM_D13 D9 2.5-V Data bus
8 FSM_D14 A11 2.5-V Data bus
9 FSM_D15 B11 2.5-V Data bus
85 SRAM_ADSCN P12 2.5-V Address status controller
84 SRAM_ADSPN J13 2.5-V Address status processor
83 SRAM_ADVN K13 2.5-V Adress valid
93 SRAM_BWAN P10 2.5-V Byte write select
94 SRAM_BWBN N11 2.5-V Byte write select
97 SRAM_CE2 — 2.5-V Chip enable 2
92 SRAM_CE3N — 2.5-V Chip enable 3
98 SRAM_CEN K11 2.5-V Chip enable 1
89 SRAM_CLK N12 2.5-V Clock
88 SRAM_GWN — 2.5-V Global write enable
31 SRAM_MODE — 2.5-V Burst sequence selection
64 SRAM_ZZ — 2.5-V Power sleep mode
Table 2–31. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Board
Reference (U37)
Schematic
Signal Name
Cyclone V GX
Pin Number
I/O Standard Description
Table 2–32. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)
Board
Reference (U18)
Schematic Signal Name
Cyclone V GX
Pin Number
I/O Standard Description
F6 FLASH_ADVN H15 2.5-V Address valid
B4 FLASH_CEN L10 2.5-V Chip enable