10/100/1000 ethernet, 10/100/1000 ethernet –26 – Altera Cyclone V GX FPGA Development Board User Manual

Page 34

Advertising
background image

2–26

Chapter 2: Board Components

Components and Interfaces

Cyclone V GX FPGA Development Board

May 2013

Altera Corporation

Reference Manual

10/100/1000 Ethernet

The development board supports 10/100/1000 base-T Ethernet using an external
Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. The
PHY-to-MAC interface employs a RGMII interface. The MAC function must be
provided in the FPGA for typical networking applications.

The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires a 25-MHz
reference clock driven from a dedicated oscillator. The PHY interfaces to a RJ45 model
with internal magnetics that can be used for driving copper lines with Ethernet traffic.

Figure 2–7

shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111

PHY.

Table 2–23

lists the Ethernet PHY interface pin assignments.

A25

PCIE_TX_P2

AB4

1.5-V PCML

Transmit bus

A26

PCIE_TX_N2

AB3

1.5-V PCML

Transmit bus

A29

PCIE_TX_P3

Y4

1.5-V PCML

Transmit bus

A30

PCIE_TX_N3

Y3

1.5-V PCML

Transmit bus

B11

PCIE_WAKEn

Y27

2.5-V

Wake signal

Table 2–22. PCI Express Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J19)

Schematic Signal Name

Cyclone V GX

Pin Number

I/O Standard

Description

Figure 2–7. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY

10/100/1000 Mbps

Ethernet MAC

Marvell 88E1111

PHY

Device

Transformer

RJ45

RGMII Interface

TXD[3:0]

RXD[3:0]

CAT 5 UTP:
- 10BASE-T
- 100BASE-TX
- 1000BASE-T

Table 2–23. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference (U10)

Schematic Signal Name

Cyclone V GX

Pin Number

I/O Standard

Description

8

ENET_GTX_CLK

U9

2.5-V CMOS

125-MHz RGMII transmit clock

23

ENET_INTN

B17

2.5-V CMOS

Management bus interrupt

60

ENET_LED_DUPLEX

2.5-V CMOS

Duplex or collision LED. Not used

70

ENET_LED_DUPLEX

2.5-V CMOS

Duplex or collision LED. Not used

76

ENET_LED_LINK10

2.5-V CMOS

10-Mb link LED

74

ENET_LED_LINK100

2.5-V CMOS

100-Mb link LED

73

ENET_LED_LINK1000

2.5-V CMOS

1000-Mb link LED

58

ENET_LED_RX

2.5-V CMOS

RX data active LED

69

ENET_LED_RX

2.5-V CMOS

RX data active LED

68

ENET_LED_TX

2.5-V CMOS

TX data active LED

25

ENET_MDC

C17

2.5-V CMOS

Management bus data clock

Advertising