Altera Cyclone V GX FPGA Development Board User Manual
Page 15
Chapter 2: Board Components
2–7
MAX V CPLD 5M2210 System Controller
May 2013
Altera Corporation
Cyclone V GX FPGA Development Board
Reference Manual
P9
EXTRA_SIG1
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
M8
EXTRA_SIG2
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
P15
FACTORY_LOAD
2.5-V
DIP switch to load factory or user design at power-up
R14
FACTORY_REQUEST
2.5-V
Embedded USB-Blaster II request to send FACTORY
command
N12
FACTORY_STATUS
2.5-V
Embedded USB-Blaster II FACTORY command status
E12
FAN_FORCE_ON
2.5-V
DIP switch to on or off the fan
T5
FLASH_ADVN
2.5-V
FSM bus flash memory address valid
P7
FLASH_CEN
2.5-V
FSM bus flash memory chip enable
M6
FLASH_CLK
2.5-V
FSM bus flash memory clock
N6
FLASH_OEN
2.5-V
FSM bus flash memory output enable
N7
FLASH_RDYBSYN
2.5-V
FSM bus flash memory ready
R6
FLASH_RESETN
2.5-V
FSM bus flash memory reset
R5
FLASH_WEN
2.5-V
FSM bus flash memory write enable
H13
FPGA_CONF_DONE
2.5-V
FPGA configuration done LED
H16
FPGA_CONFIG_D0
2.5-V
FPGA configuration data
G15
FPGA_CONFIG_D1
2.5-V
FPGA configuration data
H15
FPGA_CONFIG_D2
2.5-V
FPGA configuration data
C15
FPGA_CONFIG_D3
2.5-V
FPGA configuration data
E16
FPGA_CONFIG_D4
2.5-V
FPGA configuration data
D16
FPGA_CONFIG_D5
2.5-V
FPGA configuration data
F14
FPGA_CONFIG_D6
2.5-V
FPGA configuration data
E15
FPGA_CONFIG_D7
2.5-V
FPGA configuration data
G13
FPGA_CONFIG_D8
2.5-V
FPGA configuration data
H14
FPGA_CONFIG_D9
2.5-V
FPGA configuration data
D15
FPGA_CONFIG_D10
2.5-V
FPGA configuration data
G16
FPGA_CONFIG_D11
2.5-V
FPGA configuration data
F16
FPGA_CONFIG_D12
2.5-V
FPGA configuration data
E14
FPGA_CONFIG_D13
2.5-V
FPGA configuration data
J13
FPGA_CONFIG_D14
2.5-V
FPGA configuration data
F15
FPGA_CONFIG_D15
2.5-V
FPGA configuration data
M13
FPGA_CVP_CONFDONE
2.5-V
FPGA configuration via protocol done LED
P4
FPGA_DCLK
2.5-V
FPGA configuration clock
L14
FPGA_NCONFIG
2.5-V
FPGA configuration active
P5
FPGA_NSTATUS
2.5-V
FPGA configuration ready
J14
FPGA_PR_DONE
2.5-V
FPGA partial reconfiguration done
M15
FPGA_PR_ERROR
2.5-V
FPGA partial reconfiguration error
D13
FPGA_PR_READY
2.5-V
FPGA partial reconfiguration ready
F13
FPGA_PR_REQUEST
2.5-V
FPGA partial reconfiguration request
Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 2 of 5)
Board
Reference (U12)
Schematic Signal Name
I/O Standard
Description