Altera Cyclone V GX FPGA Development Board User Manual
Page 52
2–44
Chapter 2: Board Components
Memory
Cyclone V GX FPGA Development Board
May 2013
Altera Corporation
Reference Manual
E6
FLASH_CLK
M9
2.5-V
Clock
F8
FLASH_OEN
M8
2.5-V
Output enable
F7
FLASH_RDYBSYN
L11
2.5-V
Ready
D4
FLASH_RESETN
L9
2.5-V
Reset
G8
FLASH_WEN
J15
2.5-V
Write enable
C6
FLASH_WPN
—
2.5-V
Write protect
A1
FSM_A1
N10
2.5-V
Address bus
B1
FSM_A2
N9
2.5-V
Address bus
C1
FSM_A3
M12
2.5-V
Address bus
D1
FSM_A4
M11
2.5-V
Address bus
D2
FSM_A5
G7
2.5-V
Address bus
A2
FSM_A6
G8
2.5-V
Address bus
C2
FSM_A7
F6
2.5-V
Address bus
A3
FSM_A8
G6
2.5-V
Address bus
B3
FSM_A9
J10
2.5-V
Address bus
C3
FSM_A10
K10
2.5-V
Address bus
D3
FSM_A11
E6
2.5-V
Address bus
C4
FSM_A12
E7
2.5-V
Address bus
A5
FSM_A13
D6
2.5-V
Address bus
B5
FSM_A14
D7
2.5-V
Address bus
C5
FSM_A15
A2
2.5-V
Address bus
D7
FSM_A16
A3
2.5-V
Address bus
D8
FSM_A17
D8
2.5-V
Address bus
A7
FSM_A18
E8
2.5-V
Address bus
B7
FSM_A19
F8
2.5-V
Address bus
C7
FSM_A20
G9
2.5-V
Address bus
C8
FSM_A21
H9
2.5-V
Address bus
A8
FSM_A22
J9
2.5-V
Address bus
G1
FSM_A23
H7
2.5-V
Address bus
H8
FSM_A24
J7
2.5-V
Address bus
B6
FSM_A25
A4
2.5-V
Address bus
B8
FSM_A26
A5
2.5-V
Address bus
F2
FSM_D0
E13
2.5-V
Data bus
E2
FSM_D1
F13
2.5-V
Data bus
G3
FSM_D2
C6
2.5-V
Data bus
E4
FSM_D3
C7
2.5-V
Data bus
E5
FSM_D4
A6
2.5-V
Data bus
G5
FSM_D5
B6
2.5-V
Data bus
G6
FSM_D6
A8
2.5-V
Data bus
Table 2–32. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board
Reference (U18)
Schematic Signal Name
Cyclone V GX
Pin Number
I/O Standard
Description