Altera Cyclone V GX FPGA Development Board - Manual (Page 14)

2–6 Chapter 2: Board Components
MAX V CPLD 5M2210 System Controller
Cyclone V GX FPGA Development Board May 2013 Altera Corporation
Reference Manual
MAX V CPLD 5M2210 System Controller
The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the
following purposes:
■ FPGA configuration from flash
■ Power measurement
■ Control and status registers for remote system update
Figure 2–2 illustrates the MAX V CPLD 5M2210 System Controller's functionality and
external circuit connections as a block diagram.
Table 2–4 lists the I/O signals present on the MAX V CPLD 5M2210 System
Controller. The signal names and functions are relative to the MAX V device.
Figure 2–2. MAX V CPLD 5M2210 System Controller Block Diagram
Information
Register
Embedded
USB-Blaster II
Si571
Controller
Si5538
Controller
SLD-HUB
PFL
FSM Bus
MAX V CPLD System Controller
Power
Measurement
Results
Virtual-JTAG
PC
FPGA
LTC2418
Controller
Flash
Decoder Encoder
GPIO
JTAG Control
SSRAM Control
Register
Si571
Programmable
Oscillator
Si5338
Programmable
Oscillator
Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 1 of 5)
Board
Reference (U12)
Schematic Signal Name I/O Standard Description
N4 5M2210_JTAG_TMS 2.5-V MAX V JTAG TMS
E13 CLK50_EN 2.5-V 50 MHz oscillator enable
J5 CLK_CONFIG 2.5-V 100 MHz configuration clock input
N14 CLK_ENABLE 2.5-V DIP switch for clock oscillator enable
N15 CLK_SEL 2.5-V DIP switch for clock select—SMA or oscillator
J12 CLKIN_50_MAXV 2.5-V 50 MHz clock input
L5 CLOCK_SCL 2.5-V Programmable oscillator I 2 C clock
K4 CLOCK_SDA 2.5-V Programmable oscillator I 2 C data
R7 CPU_RESETN 2.5-V FPGA reset push button
M16 EXTRA_SIG0 2.5-V Embedded USB-Blaster II interface. Reserved for future use