Altera Cyclone V GX FPGA Development Board - Manual (Page 31)

Chapter 2: Board Components 2–23
General User Input/Output
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
Table 2–20 lists the LCD pin definitions, and is an excerpt from Lumex data sheet.
f
For more information such as timing, character maps, interface guidelines, and other
related documentation, visit
www.lumex.com .
Debug Header
This development board includes a 2×7 debug header for debug purposes. The FPGA
I/Os route directly to the header for design testing, debugging, or quick verification.
Table 2–21 summarizes the debug header pin assignments, signal names, and
functions.
Table 2–20. LCD Pin Definitions and Functions
Pin
Number
Symbol
Level
Function
1 V
DD
—
Power supply
5 V
2 V
SS
— GND (0 V)
3 V
0
— For LCD drive
4 RS H/L
Register select signal
H: Data input
L: Instruction input
5 R/W H/L
H: Data read (module to MPU)
L: Data write (MPU to module)
6 E H, H to L Enable
7–14 DB0–DB7 H/L Data bus—software selectable 4-bit or 8-bit mode
Table 2–21. Debug Header Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (J14)
Schematic Signal
Name
Cyclone V GX
Pin Number
I/O Standard Description
1 DEBUG_HDR0 E10 2.5-V Single-ended signal for debug purposes only
2 DEBUG_HDR6 U22 1.5-V Single-ended signal for debug purposes only
5 DEBUG_HDR2 L21 1.5-V Single-ended signal for debug purposes only
8 DEBUG_HDR9 M21 1.5-V Single-ended signal for debug purposes only
11 SECURITY_CPLD_MRn — 1.5-V Test signal