Altera Cyclone V GX FPGA Development Board - Manual (Page 41)

Chapter 2: Board Components 2–33
Memory
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
Table 2–28 summarizes the SDI video input interface pin assignments, signal names,
and functions.
Memory
This section describes the development board’s memory interface support and also
their signal names, types, and connectivity relative to the Cyclone V GX. The
development board has the following memory interfaces:
■ DDR3 SDRAM
■ Synchronous SRAM
■ Synchronous flash
f
For more information about the memory interfaces, refer to the following documents:
■ Timing Analysis section in the External Memory Interface Handbook.
■ DDR, DDR2, and DDR3 SDRAM Design Tutorials section in the External Memory
Interface Handbook.
DDR3 SDRAM
The development board supports four 16Mx16x8 and two16Mx8x8 DDR3 SDRAM
interfaces for very high-speed sequential memory access. The DDR3 SDRAM has two
independent interfaces:
■ DDR3A x32 interface using a hard memory controller (vertical I/O banks on the
bottom edge of the FPGA).
■ DDR3B x32 interface using a soft memory controller (horizontal I/O banks on the
right edge of the FPGA).
Each 32-bit data bus comprises of two x16 devices and one x8 device for ECC support.
With a soft memory controller, this memory interface runs at a target frequency of
333 MHz for a maximum theoretical bandwidth of over 21.31 Gbps. The maximum
frequency for this DDR3 device is 667 MHz with a CAS latency of 9.
Table 2–28. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (U4)
Schematic
Signal Name
Cyclone V GX
Pin Number
I/O Standard Description
7 SDI_RX_BYPASS AF10 2.5-V Equalizer bypass enable
10 SDI_RX_N W1 1.5-V PCML Serial data output N
11 SDI_RX_P W2 1.5-V PCML Serial data output P
14 SDI_RX_EN AE10 2.5-V Device enable