Altera Cyclone V GX FPGA Development Board - Manual (Page 35)

Chapter 2: Board Components 2–27
Components and Interfaces
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
HSMC
The development board supports a HSMC interface. This physical interface provides
four channels of 3.125 Gbps-capable transceivers. The HSMC interface also supports a
full SPI4.2 interface (17 LVDS channels), three input and output clocks, as well as
JTAG and SMB signals. The LVDS channels can be used for CMOS signaling or LVDS.
1
The HSMC is an Altera-developed open specification, which allows you to expand
the functionality of the development board through the addition of daughtercards
(HSMCs).
f
For more information about the HSMC specification such as signaling standards,
signal integrity, compatible connectors, and mechanical information, refer to the
High
Speed Mezzanine Card (HSMC) Specification manual.
24 ENET_MDIO D18 2.5-V CMOS Management bus data
28 ENET_RESETN J17 2.5-V CMOS Device reset
2 ENET_RX_CLK G17 2.5-V CMOS RGMII receive clock
95 ENET_RX_D0 AF8 2.5-V CMOS RGMII receive data bus
92 ENET_RX_D1 AB9 2.5-V CMOS RGMII receive data bus
93 ENET_RX_D2 AA9 2.5-V CMOS RGMII receive data bus
91 ENET_RX_D3 AH7 2.5-V CMOS RGMII receive data bus
94 ENET_RX_DV D19 2.5-V CMOS RGMII receive data valid
11 ENET_TX_D0 AG7 2.5-V CMOS RGMII transmit data bus
12 ENET_TX_D1 AB8 2.5-V CMOS RGMII transmit data bus
14 ENET_TX_D2 AA8 2.5-V CMOS RGMII transmit data bus
16 ENET_TX_D3 AG8 2.5-V CMOS RGMII transmit data bus
9 ENET_TX_EN K20 2.5-V CMOS RGMII transmit enable
55 ENET_XTAL_25MHZ — 2.5-V CMOS 25-MHz RGMII transmit clock
29 MDI_P0 — 2.5-V CMOS Media dependent interface
31 MDI_N0 — 2.5-V CMOS Media dependent interface
33 MDI_P1 — 2.5-V CMOS Media dependent interface
34 MDI_N1 — 2.5-V CMOS Media dependent interface
39 MDI_P2 — 2.5-V CMOS Media dependent interface
41 MDI_N2 — 2.5-V CMOS Media dependent interface
42 MDI_P3 — 2.5-V CMOS Media dependent interface
43 MDI_N3 — 2.5-V CMOS Media dependent interface
Table 2–23. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 2 of 2)
Board
Reference (U10)
Schematic Signal Name
Cyclone V GX
Pin Number
I/O Standard Description