Altera Cyclone V GX FPGA Development Board - Manual (Page 40)

2–32 Chapter 2: Board Components
Components and Interfaces
Cyclone V GX FPGA Development Board May 2013 Altera Corporation
Reference Manual
Table 2–26 summarizes the SDI video output interface pin assignments, signal names,
and functions.
The cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD, and 2.97 Gbit
dual-link HD modes. Control signals are allowed for bypassing or disabling the
device, as well as a carrier detect or auto-mute signal interface.
Table 2–27 lists the cable equalizer lengths.
Figure 2–9 shows the SDI cable equalizer, which is an excerpt from the LMH0384
cable equalizer data sheet. On this development board, the output is a single-ended
output, with the negative channel driving a load local to the board.
Table 2–26. SDI Video Output Interface Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (U1)
Schematic
Signal Name
Cyclone V GX
Pin Number
I/O Standard Description
1 SDI_TX_P V4 1.5-V PCML Serial data input P
2 SDI_TX_N V3 1.5-V PCML Serial data input N
4 SDI_TX_RSET — 2.5-V Output swing set resistor
6 SDI_TX_EN AJ1 2.5-V Output driver enable
7 SDI_SDA R20 2.5-V Cable driver I 2 C bus
8 SDI_SCL T21 2.5-V Cable driver I 2 C bus
10 SDI_TX_SD_HDN AF7 2.5-V High-definition select
11 SDI_TXDRV_N — 2.5-V Serial data
12 SDI_TXDRV_P — 2.5-V Serial data
13 SDI_FAULT F25 2.5-V Data transmission fault
Table 2–27. SDI Cable Equalizer Lengths
Data Rate (Mbps) Cable Type Maximum Cable Length (m)
270
Belden 1694A
400
1485 140
2970 120
Figure 2–9. SDI Cable Equalizer
BYPASS
MUTE
REF
1.0 μF
75 Ω 37.4 Ω
1.0 μF
1.0 μF
CD
SDI
SDI
SDO
SDO
CD
MUTE
MUTE
REF
BYPASS
AEC+ AEC–
75 Ω
MUTE
Coaxial Cable
SDI Adaptive
Cable Equalizer
To FPGA
5.6 nH