Altera Cyclone V GX FPGA Development Board - Manual (Page 12)

2–4 Chapter 2: Board Components
Board Overview
Cyclone V GX FPGA Development Board May 2013 Altera Corporation
Reference Manual
S1 MAX V reset push button Reset the MAX V CPLD 5M2210 System Controller.
S3, S4, S5 General user push buttons Three user push buttons. Driven low when pressed.
Memory Devices
U6, U15, U21,
U22, U19, U23
DDR3 x32 memory
Four 128-MB DDR3 SDRAM with a 16-bit data bus and two 128-MB
DDR3 SDRAM with a 8-bit data bus.
U37 SSRAM x16 memory
18-MB standard synchronous RAM with a 12-bit data bus and 4-bit
parity.
U18 Flash x16 memory
512-MB synchronous flash devices with a 16-bit data bus for
non-volatile memory.
Communication Ports
J19 PCI Express edge connector
Gold-plated edge fingers connector for up to ×8 signaling in Gen1
mode.
J1 HSMC port
Provides eight transceiver channels and 84 CMOS or 17 LVDS
channels per the HSMC specification.
J11 Gigabit Ethernet port
RJ-45 connector which provides a 10/100/1000 Ethernet connection
via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed
Ethernet MegaCore function in RGMII mode.
Video and Display Ports
J18 Character LCD
Connector that interfaces to a provided 16 character × 2 line LCD
module along with two standoffs.
J5, J10 SDI video port
Two 75- Ω sub-miniature version B (SMB) connectors that provide a
full-duplex SDI interface through a LMH0303 cable driver and
LMH0384 cable equalizer.
Power Supply
J19 PCI Express edge connector
Interfaces to a PCI Express root port such as an appropriate PC
motherboard.
J9 DC input jack
Accepts a 14–20-V DC power supply. Do not use this input jack while
the board is plugged into a PCI Express slot.
SW1 Power switch
Switch to power on or off the board when power is supplied from the
DC input jack.
Table 2–1. Board Components (Part 3 of 3)
Board Reference Type Description