Altera Cyclone V GX FPGA Development Board - Manual (Page 33)

Chapter 2: Board Components 2–25
Components and Interfaces
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
Figure 2–6 shows the PCI Express reference clock levels.
The JTAG and SMB are optional signals in the PCI Express specification. Both types of
signals are wired to the Cyclone V GX but are not required for normal operation.
Table 2–22 summarizes the PCI Express pin assignments. The signal names and
directions are relative to the Cyclone V GX.
Figure 2–6. PCI Express Reference Clock Levels
V MAX = 1.15 V
V CROSS MAX = 550 mV
V CROSS MIN = 250 mV
V MIN = –0.30 V
REFCLK –
REFCLK +
Table 2–22. PCI Express Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (J19)
Schematic Signal Name
Cyclone V GX
Pin Number
I/O Standard Description
A5 PCIE_JTAG_TCK — LVTTL JTAG chain clock
A6 PCIE_JTAG_TDI — LVTTL JTAG chain data in
A7 PCIE_JTAG_TDO — LVTTL JTAG chain data out
A8 PCIE_JTAG_TMS — LVTTL JTAG chain mode select
A11 PCIE_PERSTN W27 LVTTL Reset
A1 PCIE_PRSNT1N — LVTTL Link width DIP switch
B17 PCIE_PRSNT2N_X1 — LVTTL Hot plug present detect
B31 PCIE_PRSNT2N_X4 — LVTTL Hot plug present detect
A13 PCIE_REFCLK_P W8 HCSL Reference clock input
A14 PCIE_REFCLK_N W7 HCSL Reference clock input
B14 PCIE_RX_P0 AG2 1.5-V PCML Receive bus
B15 PCIE_RX_N0 AG1 1.5-V PCML Receive bus
B19 PCIE_RX_P1 AE2 1.5-V PCML Receive bus
B20 PCIE_RX_N1 AE1 1.5-V PCML Receive bus
B23 PCIE_RX_P2 AC2 1.5-V PCML Receive bus
B24 PCIE_RX_N2 AC1 1.5-V PCML Receive bus
B27 PCIE_RX_P3 AA2 1.5-V PCML Receive bus
B28 PCIE_RX_N3 AA1 1.5-V PCML Receive bus
B5 PCIE_SMBCLK R11 2.5-V SMB clock
B6 PCIE_SMBDAT V22 2.5-V SMB data
A16 PCIE_TX_P0 AF4 1.5-V PCML Transmit bus
A17 PCIE_TX_N0 AF3 1.5-V PCML Transmit bus
A21 PCIE_TX_P1 AD4 1.5-V PCML Transmit bus
A22 PCIE_TX_N1 AD3 1.5-V PCML Transmit bus