Altera Cyclone V GX FPGA Development Board - Manual (Page 50)

2–42 Chapter 2: Board Components
Memory
Cyclone V GX FPGA Development Board May 2013 Altera Corporation
Reference Manual
Synchronous SRAM
The development board supports a 18-MB standard synchronous SRAM for
instruction and data storage with low-latency random access capability. The device
has a 1024K x 18-bits interface. This device is part of the shared FSM bus that connects
to the flash memory, SRAM, and MAX V CPLD 5M2210 System Controller.
The device speed is 200 MHz single-data-rate. There is no minimum speed for this
device. The theoretical bandwidth of this interface is 3.2 Gbps for continuous bursts.
The read latency for any address is two clocks while the write latency is one clock.
Table 2–31 lists the SSRAM pin assignments, signal names, and functions.
Table 2–31. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board
Reference (U37)
Schematic
Signal Name
Cyclone V GX
Pin Number
I/O Standard Description
86 FLASH_OEN M8 2.5-V Output enable
87 FLASH_WEN J15 2.5-V Write enable
37 FSM_A1 N10 2.5-V Address bus
36 FSM_A2 N9 2.5-V Address bus
44 FSM_A3 M12 2.5-V Address bus
42 FSM_A4 M11 2.5-V Address bus
34 FSM_A5 G7 2.5-V Address bus
47 FSM_A6 G8 2.5-V Address bus
43 FSM_A7 F6 2.5-V Address bus
46 FSM_A8 G6 2.5-V Address bus
45 FSM_A9 J10 2.5-V Address bus
35 FSM_A10 K10 2.5-V Address bus
32 FSM_A11 E6 2.5-V Address bus
33 FSM_A12 E7 2.5-V Address bus
50 FSM_A13 D6 2.5-V Address bus
48 FSM_A14 D7 2.5-V Address bus
100 FSM_A15 A2 2.5-V Address bus
99 FSM_A16 A3 2.5-V Address bus
82 FSM_A17 D8 2.5-V Address bus
80 FSM_A18 E8 2.5-V Address bus
49 FSM_A19 F8 2.5-V Address bus
81 FSM_A20 G9 2.5-V Address bus
39 FSM_A21 H9 2.5-V Address bus
58 FSM_D0 E13 2.5-V Data bus
59 FSM_D1 F13 2.5-V Data bus
62 FSM_D2 C6 2.5-V Data bus
63 FSM_D3 C7 2.5-V Data bus
68 FSM_D4 A6 2.5-V Data bus
69 FSM_D5 B6 2.5-V Data bus