Altera Cyclone V GX FPGA Development Board - Manual (Page 47)

Chapter 2: Board Components 2–39
Memory
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
C3 DDR3B_DQ9 D28 1.5-V SSTL Class I Data bus byte lane 1
C8 DDR3B_DQ10 A29 1.5-V SSTL Class I Data bus byte lane 1
C2 DDR3B_DQ11 H25 1.5-V SSTL Class I Data bus byte lane 1
A7 DDR3B_DQ12 H24 1.5-V SSTL Class I Data bus byte lane 1
A2 DDR3B_DQ13 H26 1.5-V SSTL Class I Data bus byte lane 1
B8 DDR3B_DQ14 B28 1.5-V SSTL Class I Data bus byte lane 1
A3 DDR3B_DQ15 D27 1.5-V SSTL Class I Data bus byte lane 1
F3 DDR3B_DQS_P0 N21
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 0
G3 DDR3B_DQS_N0 M22
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 0
C7 DDR3B_DQS_P1 P20
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 1
B7 DDR3B_DQS_N1 N20
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 1
K1 DDR3B_ODT V29 1.5-V SSTL Class I On-die termination enable
J3 DDR3B_RASN T29 1.5-V SSTL Class I Row address select
T2 DDR3B_RESETN AB27 1.5-V SSTL Class I Reset
L3 DDR3B_WEN T28 1.5-V SSTL Class I Write enable
L8 DDR3B_ZQ01 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3 x16 (U15)
N3 DDR3B_A0 Y30 1.5-V SSTL Class I Address bus
P7 DDR3B_A1 R28 1.5-V SSTL Class I Address bus
P3 DDR3B_A2 AA29 1.5-V SSTL Class I Address bus
N2 DDR3B_A3 W29 1.5-V SSTL Class I Address bus
P8 DDR3B_A4 U23 1.5-V SSTL Class I Address bus
P2 DDR3B_A5 AA30 1.5-V SSTL Class I Address bus
R8 DDR3B_A6 R23 1.5-V SSTL Class I Address bus
R2 DDR3B_A7 AC30 1.5-V SSTL Class I Address bus
T8 DDR3B_A8 T23 1.5-V SSTL Class I Address bus
R3 DDR3B_A9 AB29 1.5-V SSTL Class I Address bus
L7 DDR3B_A10 R30 1.5-V SSTL Class I Address bus
R7 DDR3B_A11 R26 1.5-V SSTL Class I Address bus
N7 DDR3B_A12 T25 1.5-V SSTL Class I Address bus
T3 DDR3B_A13 AD29 1.5-V SSTL Class I Address bus
M2 DDR3B_BA0 W30 1.5-V SSTL Class I Bank address bus
N8 DDR3B_BA1 T24 1.5-V SSTL Class I Bank address bus
M3 DDR3B_BA2 V30 1.5-V SSTL Class I Bank address bus
K3 DDR3B_CASN T30 1.5-V SSTL Class I Row address select
Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board Reference
Schematic
Signal Name
Cyclone V GX
Pin Number
I/O Standard Description