Altera Cyclone V GX FPGA Development Board - Manual (Page 27)

Chapter 2: Board Components 2–19
Clock Circuitry
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
Table 2–11 lists the oscillators, its I/O standard, and voltages required for the
development board.
Off-Board Clock Input/Output
The development board has input and output clocks which can be driven onto the
board. The output clocks can be programmed to different levels and I/O standards
according to the FPGA device’s specification.
Table 2–12 lists the clock inputs for the development board.
Table 2–11. On-Board Oscillators
Source Schematic Signal Name Frequency I/O Standard
Cyclone V GX
Pin Number
Application
X4
CLKIN_50_7A
50.000 MHz Single-Ended
H17
Top edge
CLKIN_50_TOP K15
X1 CLK_CONFIG 100.000 MHz 2.5V CMOS — Fast FPGA configuration
J19
PCIE_REFCLK_P
100.000 MHz LVDS
W8
PCI Express x4
PCIE_REFCLK_N W7
U25
CLKIN_BANK3B_125_R_P
125.000 MHz
1.5V LVDS
(fanout
buffer)
Y15
Bottom edge
CLKIN_BANK3B_125_R_N AA15
CLKIN_BANK4A_125_R_P AC15
CLKIN_BANK4A_125_R_N AB16
REFCLK1_Q2L_P P8
HSMC port A
REFCLK1_Q2L_N N7
X2
CLK_148_P
148.500 MHz LVDS
R8
HD-SDI video
CLK_148_N R7
Table 2–12. Off-Board Clock Inputs
Source
Schematic Signal
Name
I/O Standard
Cyclone V GX
Pin Number
Description
SMA
CLKIN_SMA_P LVPECL —
Input to LVDS fan-out buffer (drives one REFCLK)
CLKIN_SMA_N LVPECL —
Samtec HSMC HSMA_CLK_IN0 2.5-V L15
Single-ended input from the installed HSMC cable
or board.
Samtec HSMC
HSMA_CLK_IN_P1 LVDS/2.5-V H19 LVDS input from the installed HSMC cable or
board. Can also support 2x LVTTL inputs.
HSMA_CLK_IN_N1 LVDS/LVTTL J18
Samtec HSMC
HSMA_CLK_IN_P2 LVDS/LVTTL L14 LVDS input from the installed HSMC cable or
board. Can also support 2x LVTTL inputs.
HSMA_CLK_IN_N2 LVDS/LVTTL L13
PCI Express
Edge PCIE_REFCLK_P LVDS W8
LVDS input from the PCI Express edge connector.
PCIE_REFCLK_N HCSL W7