Altera Cyclone V GX FPGA Development Board - Manual (Page 25)

Chapter 2: Board Components 2–17
Setup Elements
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
PCI Express Link Width DIP Switch
The PCI Express link width DIP switch (SW4) enable or disable different link width
configurations.
Table 2–10 lists the switch controls and descriptions.
CPU Reset Push Button
The CPU reset push button, CPU_RESETn (S2), is an input to the Cyclone V GX DEV_CLRn
pin and is an open-drain I/O from the MAX V CPLD System Controller. This push
button is the default reset for both the FPGA and CPLD logic. The MAX V CPLD
5M2210 System Controller also drives this push button during power-on-reset (POR).
MAX V Reset Push Button
The MAX V reset push button, MAX_RESETn (S1), is an input to the MAX V CPLD
5M2210 System Controller. This push button is the default reset for the CPLD logic.
Program Configuration Push Button
The program configuration push button, PGM_CONFIG (S6), is an input to the MAX V
CPLD 5M2210 System Controller. This input forces a FPGA reconfiguration from the
flash memory. The location in the flash memory is based on the settings of
PGM_LED[2:0]
, which is controlled by the program select push button, PGM_SEL. Valid
settings include PGM_LED0, PGM_LED1, or PGM_LED2 on the three pages in flash memory
reserved for FPGA designs.
Program Select Push Button
The program select push button, PGM_SEL (S7), is an input to the MAX V CPLD System
Controller. This push button toggles the PGM_LED[2:0]sequence that selects which
location in the flash memory is used to configure the FPGA. Refer to
Table 2–6 for the
PGM_LED[2:0] sequence definitions.
3 PCIE_JTAG_EN
ON : Bypass PCI Express edge connector
OFF : PCI Express edge connector in-chain
ON
4 NC Not used —
Table 2–9. JTAG Chain Control DIP Switch
Switch Schematic Signal Name Description Default
Table 2–10. PCI Express Link Width DIP Switch Controls
Switch Schematic Signal Name Description Default
1 PCIE_PRSNT2n_x1
ON : Enable x1 presence detect
OFF : Disable x1 presence detect
OFF
2 PCIE_PRSNT2n_x4
ON : Enable x4 presence detect
OFF : Disable x4 presence detect
OFF
3 NC Not used —
4 FAN_FORCE_ON
ON : Enable fan
OFF : Disable fan
OFF