Figure 7-5, Partial destination address (da) match, Rx legacy traffic i/f – Xilinx IP Ethernet AVB Endpoint v2.4 UG492 User Manual

Page 71: Match pattern register match enable register

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Figure 7-5, Partial destination address (da) match, Rx legacy traffic i/f | Match pattern register match enable register | Xilinx IP Ethernet AVB Endpoint v2.4 UG492 User Manual | Page 71 / 172 Figure 7-5, Partial destination address (da) match, Rx legacy traffic i/f | Match pattern register match enable register | Xilinx IP Ethernet AVB Endpoint v2.4 UG492 User Manual | Page 71 / 172
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