Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 10)

10 www.xilinx.com Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Chapter 9: Precise Timing Protocol Packet Buffers
Figure 9-1: Tx PTP Packet Buffer Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 9-2: Rx PTP Packet Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Chapter 10: Configuration and Status
Figure 10-1: Single Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 10-2: Single Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 10-3: PLB Address Space of the Ethernet AVB Endpoint Core and Connected
Tri-Mode Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Chapter 11: Constraining the Core
Chapter 12: System Integration
Figure 12-1: Connection to the Tri-Mode Ethernet MAC Core
(without Ethernet Statistics) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 12-2: Connection to the Tri-Mode Ethernet MAC and Ethernet Statistic Cores 115
Figure 12-3: Connection to the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC
(without Ethernet Statistics) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 12-4: Connection to the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC
and Ethernet Statistic Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 12-5: Connection of the Ethernet AVB Endpoint Core into an Embedded
Processor Sub-system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 12-6: Connection into an Embedded Processor Sub-system with an EDK
Top-level Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 12-7: Connection into an Embedded Processor Sub-system with an ISE
Software Top-Level Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 12-8: Connection of the Ethernet AVB Endpoint Core into an Embedded
Processor Sub-system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 12-9: Connection to the XPS LocalLink Tri-Mode Ethernet MAC . . . . . . . . . . . . 127
Chapter 13: Software Drivers
Chapter 14: Quick Start Example Design
Figure 14-1: Ethernet AVB Endpoint Example Design and Test Bench . . . . . . . . . . . . . 138
Figure 14-2: Ethernet AVB Endpoint Core Customization Screen . . . . . . . . . . . . . . . . . . 140
Chapter 15: Detailed Example Design (Standard Format)
Figure 15-1: Example Design HDL for the Ethernet AVB Endpoint . . . . . . . . . . . . . . . . 152
Figure 15-2: Ethernet AVB Endpoint Demonstration Test Bench . . . . . . . . . . . . . . . . . . 156
Figure 15-3: Simulator Wave Window Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158