Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 17)

Ethernet AVB Endpoint User Guide www.xilinx.com 17
UG492 September 21, 2010
Preface
About This Guide
The LogiCORE™ IP Ethernet AVB User Guide provides information about the Ethernet
Audio Video Bridging (AVB) Endpoint core, including how to customize, generate, and
implement the core in supported Xilinx FPGA families.
Guide Contents
This guide contains the following chapters:
• Preface, “About this Guide” introduces the organization and purpose of this guide
and the conventions used in this document.
• Chapter 1, “Introduction” introduces the core and provides related information
including additional core resources, technical support, and how to submit feedback to
Xilinx.
• Chapter 2, “Licensing the Core,” describes the available license options for the core
and how to obtain them.
• Chapter 3, “Overview of Ethernet Audio Video Bridging” provides an overview of
Ethernet Audio Video Bridging, including relevant specifications and a typical
implementation.
• Chapter 4, “Generating the Core” provides information about generating and
customizing the core using the CORE Generator™ software.
• Chapter 5, “Core Architecture” describes the major functional blocks of the Ethernet
AVB Endpoint core.
•
Chapter 6, “Ethernet AVB Endpoint Transmission” describes data transmission over
an AVB network.
• Chapter 7, “Ethernet AVB Endpoint Reception” describes data reception over an AVB
network.
• Chapter 8, “Real Time Clock and Time Stamping” describes two components that are
partially responsible for the AVB timing synchronization protocol.
•
Chapter 9, “Precise Timing Protocol Packet Buffers” describes two components that
are partially responsible for the transmission and reception of Ethernet Precise Timing
Protocol frames; these frames contain the AVB timing synchronization data.
• Chapter 10, “Configuration and Status” defines general guidelines for configuring
and monitoring the Ethernet AVB Endpoint core, including an introduction to the PLB
configuration bus and a description of the core management registers.
• Chapter 11, “Constraining the Core” defines the Ethernet AVB core constraints.
• Chapter 12, “System Integration” describes the integration of the Ethernet AVB
Endpoint core into a system, including connection of the core to the Xilinx Tri-Mode
Ethernet MAC and Ethernet Statistic cores.