Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 23)

Ethernet AVB Endpoint User Guide www.xilinx.com 23
UG492 September 21, 2010
Chapter 1
Introduction
This chapter introduces the core and provides related information including
recommended design experience, additional resources, technical support, and how to
submit feedback to Xilinx.
The Ethernet AVB Endpoint core is a fully verified solution that supports Verilog-HDL and
VHDL. In addition, the example design in this guide is provided in both Verilog and
VHDL formats.
System Requirements
Windows
•
Windows XP Professional 32-bit/64-bit
•
Windows Vista Business 32-bit/64-bit Linux
•
Red Hat Enterprise Linux WS v4.0 32-bit/64-bit
• Red Hat Enterprise Desktop v5.0 32-bit/64-bit (with Workstation Option)
• SUSE Linux Enterprise (SLE) desktop and server v10.1 32-bit/64-bit
Software
• ISE® software v12.2
About the Core
The Ethernet AVB Endpoint core is available through the Xilinx CORE Generator™
software included in the latest IP Update on the Xilinx IP Center. For detailed information
about the core, see the Ethernet AVB Endpoint
product page . For information about
licensing options, see Chapter 2, “Licensing the Core.”