Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 68)

68 www.xilinx.com Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Chapter 7: Ethernet AVB Endpoint Reception
Figure 7-3 illustrates Legacy frame reception for an error free frame in which at least one of
the eight individual MAC Header Filters obtained a match (filter number 3 is illustrated as
having obtained the match in this example). Note the following:
• Each of the eight individual MAC Header Filters has a corresponding bit within the
legacy_rx_filter_match[7:0]
bus. If the corresponding MAC Header Filter
obtains a match, the relevant bit will be asserted. This will be fully aligned with the
legacy_rx_data_valid
signal during frame reception.
•
Every bit within the legacy_rx_filter_match[7:0] bus will be asserted for
frame reception in which the Frame Destination Address (DA) contained a Broadcast
Address.
•
Every bit within the legacy_rx_filter_match[7:0] bus will be asserted when
the MAC Header Filter is operating in Promiscuous Mode (see
“Rx Filtering Control
Register” ).
X-Ref Target - Figure 7-3
Figure 7-3: Normal Frame Reception: Address Filter Match
rx_clk
legacy_rx_data[7:0]
legacy_rx_data_valid
legacy_rx_frame_good
rx_clk_enable
DA SA DATA L/T
legacy_rx_filter_match[0]
legacy_rx_filter_match[3]
legacy_rx_filter_match[1]
legacy_rx_filter_match[2]
legacy_rx_filter_match[4]
legacy_rx_filter_match[5]
legacy_rx_filter_match[6]
legacy_rx_filter_match[7]
legacy_rx_frame_bad