Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 142)

142 www.xilinx.com Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Chapter 14: Quick Start Example Design
Timing Simulation
This section contains instructions for running a timing simulation of the Ethernet AVB
Endpoint core using either VHDL or Verilog. A timing simulation model is generated
when run through the Xilinx tools using the implementation script. You must implement
the core before attempting to run timing simulation.
To run a VHDL or Verilog timing simulation of the example design:
1. Run the implementation script (see “Implementing the Example Design,” page 141 ).
2. Open a command prompt or shell, then set the current directory to:
<project_dir>/<component_name>/simulation/timing/
3. Launch the simulation script:
ModelSim: vsim -do simulate_mti.do
IES: ./simulate_ncsim.sh
VCS: ./simulate_vcs.sh (Verilog only)
The simulator script compiles the gate-level model and the demonstration test bench, adds
relevant signals to a wave window, and then runs the simulation to completion. You can
then inspect the simulation transcript and waveform to observe the operation of the core.
What’s Next?
The Ethernet AVB Endpoint core can be delivered in two different formats, selectable from
page 1 the CORE Generator Customization GUI:
• Standard CORE Generator software format (provided for the standard ISE software
environment)
For detailed information about the core delivery using the Standard CORE Generator
software format, including example design information, guidelines for modifying the
design and extending the test bench, see
Chapter 15, “Detailed Example Design
(Standard Format).” .
• Generate as an EDK pcore (provided for the Embedded Development Kit)
For detailed information about the core delivery for the Embedded Developments Kit
(EDK), see
Chapter 16, “Detailed Example Design (EDK format).”