Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 141)

Ethernet AVB Endpoint User Guide www.xilinx.com 141
UG492 September 21, 2010
Implementing the Example Design
Implementing the Example Design
After the core is generated, the netlists and example design can be processed by the Xilinx
implementation tools. The generated output files include several scripts to assist you in
running the Xilinx software.
To implement the Ethernet AVB Endpoint example design core:
From the CORE Generator software project directory window, type the following:
Linux
% cd <project_dir>/<component_name>/implement
% ./implement.sh
Windows
> cd <project_dir>\<component_name>\implement
> implement.bat
These commands execute a script that synthesizes, builds, maps, and place-and-routes the
example design. The script then creates gate-level netlist HDL files in either VHDL or
Verilog, along with associated timing information (SDF) files.
Simulating the Example Design
Setting up for Simulation
To run functional and timing simulations you must have the Xilinx Simulation Libraries
compiled for your system. See the Compiling Xilinx Simulation Libraries (COMPXLIB) in
the Xilinx ISE Synthesis and Verification Design Guide, and the Xilinx ISE Software Manuals
and Help. You can download these documents from:
www.xilinx.com/support/software_manuals.htm
Functional Simulation
This section provides instructions for running a functional simulation of the Ethernet AVB
Endpoint core using either VHDL or Verilog. The functional simulation model is provided
when the core generated; implementing the core before simulation is not required.
To run a VHDL or Verilog functional simulation of the example design:
1. Open a command prompt or shell, then set the current directory to:
<project_dir>/<component_name>/simulation/functional/
2. Launch the simulation script:
ModelSim: vsim -do simulate_mti.do
IES: ./simulate_ncsim.sh
VCS: ./simulate_vcs.sh (Verilog only)
The simulation script compiles the functional simulation model, the example design files,
the demonstration test bench, and adds relevant signals to a wave window. It then runs the
simulation to completion. After completion, you can inspect the simulation transcript and
waveform to observe the operation of the core.