Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 123)

Ethernet AVB Endpoint User Guide www.xilinx.com 123
UG492 September 21, 2010
Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs
Figure 12-7 shows the implementation using an ISE® software top-level project. In this
hierarchy, the embedded processor subsystem is created using an EDK project containing
only the blocks illustrated in the EDK tool domain block. This EDK project is not the top
level of the system and is instantiated as a black box subcomponent in a standard ISE
software project as illustrated.
In this example:
• The EDK component is synthesized by the EDK tools; this block can then be left alone
(unedited)
•
All other components (for example, the Custom AV logic) can be created using a
standard ISE software project. This flow should be familiar to a wider range of
engineers than the EDK tool set.
The main advantages of this implementation hierarchy are in terms of possible faster
development turn-around for synthesis/implementation run time. This is as a result that
the EDK components will pre-exist in netlist format and do not have to be re-synthesized
for each design iteration.
A final word of explanation is required for the EDK project illustrated in Figure 12-7 . To
assign the AVB software drivers running on the MicroBlaze processor to the Ethernet AVB
Endpoint core, the plb_port pcore was created. This pcore is simply a bunch of wires to
route through all of the PLB signals through to ports of the EDK block top level. In the
Microprocessor Hardware Specification (.mhs) file, this pcore was assigned a base address
matching that of the Ethernet AVB Endpoint
“PLB Base Address” (in the generated netlist
produced by the CORE Generator software). Then the AVB software drivers were assigned
to the plb_port instance in the Microprocessor Software Specification (.mss) file.