Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 160)

160 www.xilinx.com Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Chapter 16: Detailed Example Design (EDK format)
Directory and File Contents
The core directories and their associated files are defined in the following tables.
<project directory>
The project directory contains all the CORE Generator software project files.
<project directory>/<component name>
The <component name> directory contains the release notes file provided with the core,
which may include last-minute changes and updates.
Table 16-1: Project Directory
Name Description
<project_dir>
<component_name>.ngc Top-level netlist. This is instantiated by
the Verilog or VHDL example design.
<component_name>.xco Log file that records the settings used to
generate a core. An XCO file is
generated by the CORE Generator
software for each core that it creates in
the current project directory. An XCO
file can also be used as an input to the
CORE Generator software.
<component_name>_flist.txt List of files delivered with the core.
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Table 16-2: Component Name Directory
Name Description
<project_dir>/<component_name>
eth_avb_endpoint_readme.txt Core release notes file.
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