Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 87)

Ethernet AVB Endpoint User Guide www.xilinx.com 87
UG492 September 21, 2010
Chapter 10
Configuration and Status
This chapter provides general guidelines for configuring and monitoring the Ethernet AVB
Endpoint core, including an introduction to the PLB configuration bus and a description of
the core management registers.
Processor Local Bus Interface
The Processor Local Bus (PLB) bus on the Ethernet AVB Endpoint core is designed to be
integrated directly in the Xilinx Embedded Development Kit (EDK) where it can be easily
integrated and connected to the supported embedded processors (MicroBlaze™ or
PowerPC®). As a result, the PLB interface does not require in-depth understanding and
the following information is provided for reference only. See the
EDK documentation for
further information.
The PLB interface, defined by IBM, can be complex and support many usage modes (such
as multiple bus masters). It can support single or burst read/writes, and can support
different bus widths and different peripheral bus widths.
The general philosophy of the Ethernet AVB Endpoint core has been to implement a PLB
interface which is as simple as possible. The following features are provided:
• 32-bit data width.
• Implements a simple PLB slave.
• Supports single read/writes only (no burst or page modes).
Single Read Transaction
Figure 10-1 illustrates a single read data transfer on the PLB. Note the following:
• Wait states can be added to the Address cycle by asserting Sl_wait and delaying
Sl_addrAck
.
•
Wait states can be inserted in the Read fetch by delaying the assertion of Sl_rdDAck.