Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 152)

152 www.xilinx.com Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Chapter 15: Detailed Example Design (Standard Format)
Timing Simulation
The test script is a ModelSim, IES, or VCS macro that automates the simulation of the test
bench and is in the following location:
<project_dir>/<component_name>/simulation/timing/
The test script performs the following tasks:
•
Compiles the SimPrim-based gate level netlist simulation model
•
Compiles the demonstration test bench
•
Starts a simulation of the test bench using back-annotated timing information (SDF)
•
Opens a Wave window and adds signals of interest
•
Runs the simulation to completion
Example Design
Figure 15-1 illustrates the complete example design for the Ethernet AVB Endpoint.
Individual sub-blocks are described in the following sections.
Note: The example design is designed to allow the core, in isolation, to be tested and to
demonstrate some of the functionality of the core, and does not create a realistic implementation. In
a real system the loopback module should be replaced with an Ethernet MAC, the PLB module
should be replaced with an embedded processor, and the frame stimulus and checker modules
should be replaced with the desired AV and Legacy client functionality.
X-Ref Target - Figure 15-1
Figure 15-1: Example Design HDL for the Ethernet AVB Endpoint
Example Design Top Level
PLB
module
Interrupts PLB
Ethernet
AVB
Endpoint
Core
Tx Frame
Stimulus
Tx Frame
Stimulus
Rx Frame
Checker
Rx Frame
Checker
AV Traffic
AV Traffic
Legacy
Traffic
Legacy
Traffic
Loopback
Module