Licensing the core, Before you begin, License options – Xilinx IP Ethernet AVB Endpoint v2.4 UG492 User Manual

Page 27: Simulation only, Full system hardware evaluation, Chapter 2: licensing the core, Simulation only full system hardware evaluation, Chapter 2, “licensing the core, Chapter 2

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Ethernet AVB Endpoint User Guide

www.xilinx.com

27

UG492 September 21, 2010

Chapter 2

Licensing the Core

This chapter provides instructions for obtaining a license key for the Ethernet AVB
Endpoint core, which you must do before using the core in your designs. The Ethernet AVB
Endpoint core is provided under the terms of the

Xilinx Core Site License Agreement

.

Before you Begin

This chapter assumes that you have installed the required Xilinx® ISE® Design Suite
version following the instructions provided by the Xilinx ISE Installation, Licensing and
Release Notes Guide,

www.xilinx.com/support/documentation/dt_ise.htm

. Detailed

software requirements can be found on the product web page for this core,

www.xilinx.com/products/ipcenter/DO-DI-EAVB-EPT.htm.

License Options

The Ethernet AVB Endpoint core provides three licensing options. After installing the
required ISE Design Suite version, choose a license option.

Simulation Only

The Simulation Only Evaluation license key is provided with the ISE CORE Generator tool.
This key lets you assess core functionality with either the example design provided with
the Ethernet AVB Endpoint core, or alongside your own design and allows you to
demonstrate the various interfaces to the core in simulation. (Functional simulation is
supported by a dynamically generated HDL structural model.)

Full System Hardware Evaluation

The Full System Hardware Evaluation license key is available at no cost and lets you fully
integrate the core into an FPGA design, place and route the design, evaluate timing, and
perform back-annotated gate-level simulation of the core using the demonstration test
bench provided with the core.

In addition, the license key lets you generate a bitstream from the placed and routed
design, which can then be downloaded to a supported device and tested in hardware. The
core can be tested in the target device for a limited time before timing out (ceasing to
function), at which time it can be reactivated by reconfiguring the device.

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