Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 20)

20 www.xilinx.com Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Preface: About This Guide
List of Abbreviations
The following table describes acronyms used in this manual.
Acronym Spelled Out
AV Audio Video
AVB Audio Video Bridging
BMCA Best Master Clock Algorithm
CRC Cyclic Redundancy Check
DA Destination Address
DMA Direct Memory Access
DSP Digital Signal Processor
EDK Embedded Development Kit
EMAC Ethernet MAC
FCS Frame Check Sequence
FIFO First In First Out
FPGA Field Programmable Gate Array.
Gbps Gigabits per second
GMII Gigabit Media Independent Interface
GUI Graphical User Interface
HDL Hardware Description Language
IES Incisive Unified Simulator
I/F Interface
IO Input/Output
IP Intellectual Property
ISE® Integrated Software Environment
KHz Kilo Hertz
LLDP Link Layer Discovery Protocol
MAC Media Access Controller
Mbps Megabits per second
MDIO Management Data Input/Output
MHS
Microprocessor Hardware Description: a proprietary file format,
using the .mhs file extension, for a XPS project
MHz Mega Hertz
ms milliseconds
MPMC Multi-Port Memory Controller
ns nanoseconds