Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 89)

Ethernet AVB Endpoint User Guide www.xilinx.com 89
UG492 September 21, 2010
Processor Local Bus Interface
Single Write Transaction
Figure 10-2 illustrates a single write data transfer on the PLB. Note the following:
•
Wait states can be added to the Address cycle by asserting Sl_wait and delaying
Sl_addrAck
.
• Wait states can be inserted in the Write sample by delaying the assertion of
Sl_wrDAck
.
X-Ref Target - Figure 10-2
Figure 10-2: Single Write Transaction
PLB_clk
PLB_RNW
PLB_BE[0:7]
PLB_size[0:3]
PLB_type[0:2]
PLB_abort
PLB_ABus[0:31]
PLB_AValid
SI_wait
SI_addrAck
PLB_wrDBus[0:31]
SI_wrDAck
SI_wrComp
PLB_wrBurst
SI_rdDBus[0:31]
SI_rdWrAddr[0:3]
SI_rdDAck
SI_rdComp
PLB_rdBurst
0000
0000
A0
000
11111111
0000
D(A0)