Cirrus Logic AN368 - Manual (Page 21)

AN368
AN368REV2 21
c. Trailing-edge Blanking
Configurable blanking time on the zero-current detection (ZCD) comparator provides protection to suppress
false comparator values due to noise at the falling edge of the gate drive. The controller suppresses any
comparator result from the falling edge of the gate drive to the end of the configurable trailing-edge blanking
time. The duration of the trailing-edge blanking time is set through the TEB[3:0] bits in register Config18 at
Address 50.
A setting of TEB[3:0] = 5 results in a trailing-edge blanking time of 500ns. In addition, the trailing-edge blanking
sets the minimum T2 time for the design since the ZCD comparator is ignored during the trailing-edge blanking
time.
d. Maximum Gate Drive Duration
The CS1630 controller provides configurable maximum gate duration to protect against a potential overstress
condition. The gate drive to the power FET is automatically disabled if the gate drive duration exceeds the
configurable limit in the absence of a trip of the I
Sense
comparator output. The maximum gate drive duration
T1
max
is configurable using the GD_DUR register at Address 33.
A setting of 65 for register GD_DUR provides a maximum gate drive duration time of 26.35 s. The GD_DUR
register can be set to a percentage over the gate drive duration expected for the maximum peak current within
the system.
e. Minimum Measurable Peak Current
To achieve optimum output regulation at low dim values, the minimum measurable peak current must be set.
Voltage V
IPK(min)
corresponds to the minimum peak current measurement across sense resistor R
Sense
when
FET Q4 is turned ‘ON’ and is calculated using the minimum peak current level bits IPEAK[2:0] in register
Config3 at Address 35 and the offset adjustment bits CLAMP[1:0] in register Config2 at Address 34.
Setting the voltage V
IPK(min)
to be greater than 0.7V reduces the range of output regulation. Setting the voltage
V
IPK(min)
to be less than 0.2V can increase sensitivity to noise leading to a jittery control. For the CS1630,
0.25V should be considered the lower limit. For the CS1631, 0.35V should be considered the lower limit.
f. T2 Time-out Configuration
The CS1630 controller provides a T2 time out limit to ensure a minimum switching frequency for each channel.
The T2 duration is measured from the falling edge of the gate drive to the time at which the secondary current
equals zero. The controller uses the ZCD comparator output to locate the end of the T2 duration. If the T2
duration exceeds the T2 time out limit, the current switching cycle is terminated, and the gate drive for the next
channel switching cycle initiates.
The T2 time out limit is configurable through the TIMEOUT[1:0] bits in register Config12 at Address 44.
TIMEOUT[1:0] T2 Time-out Limit
0 45ms
1 70.6ms
2 96.2ms
3 121.8ms
Table 2. T2 Time-out Limits
[Eq. 39] T
TEB
TEB[3:0]  = 2  50ns  
[Eq. 40] T1
max
GD_DUR 8    7 +   = 50  ns
[Eq. 41] V
IPK min  
1.4
IPEAK[2:0] 1 +   16    15 +   CLAMP[1:0] 8     – 8  +
512
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