Cirrus Logic AN368 - Manual (Page 65)

AN368
AN368REV2 65
4.3 Completing the Design
Step 12) Choose Power Components
The maximum drain current through transistor Q4 is limited to 297.5mA. The smallest 400V MOSFET in a
package capable of handling the power is 1A. The flyback stage output diode D15 has a peak current of
(5.57
 0.2975) = 1.66A, an average DC current of 488mA, and a max reverse voltage of
250V/5.57+32V = 77V. A 1A 90V Schottky diode meets the requirements. The boost diode D1 has a peak
current of 0.6A and an average DC current of 7.3W/200V = 36.5mA. The maximum boost drain current in
transistor Q2 is 600mA due to the attach current. A 400V 1A MOSFET is adequate.
Step 13) Bias Circuit
The initial supply voltage V
DD
applied to pin VDD is defined by Equation 65:
After startup, transistor Q1 supplies V
DD
to the device with the larger current required during normal operation.
See Equation 66:
Step 14) Boost Zero-current Detection
At the boost overvoltage point of 249V, the maximum voltage V
C11
across capacitor C11 should be less than
35V. Assuming 1V tolerance, the minimum turns ratio for L3 is calculated using Equation 67:
To comply with the largest range of dimmers at their lowest conduction angle and taking into consideration
circuit tolerances, the boost inductor auxiliary winding turns ratio should be set to 7.2.
Step 15) Enable and Tune Protection Mechanisms
All protection mechanisms are configurable to designer preference. The protection configurations for the
design example are the recommended settings for the CS1630 reference design.
a. Protection Restart
Set bit FAULT_SLOW in register Config51 at Address 83 to ‘1’ enabling slow restart and configuring the
countdown timer to 40.96ms. Set bits RESTART[5:0] in register Config51 at Address 83 to ‘011001’ which
configures the restart time T
Restart
in Equation 68:
Set bit FAULT_SHDN in register Config51 at Address 83 to ‘1’ to disable the flyback and boost stage in a fault state.
b. Overcurrent Protection
The OTP settings are configured using the following:
1. Set bit OCP in register Config47 at Address 79 to ‘0’ to enable overvoltage protection
2. Set bit OCP_LAT in register Config49 at Address 81 to ‘0’ to configure the OCP fault type as unlatched
for noise immunity reasons
3. Set bits OCP_BLANK[3:0] in register Config48 at Address 80 to ‘0000’ to configure the fixed blanking
time interval t
OCP
to 150ns, which is based on noise observed on the FBSENSE pin
4. Set bits OCP_CNT[2:0] in register Config49 at Address 81 to ‘101’ to declare an OCP fault after 5
consecutive OCP events, which was found to be a good tradeoff between noise immunity and circuit
protection
V
DD
V
Z2
V
Q2 th  
V
D6
– – =
[Eq. 138] 16.0V 3.0V – 0.7V – =
12.3V =
V
DD
V
Z2
V
Q1 th  
–   V
Z2
V
Q2 th  
V
D6
– –    =
[Eq. 139]
13.0V 12.3V  =
N
L3
N
BSTAUX
----------------------
V
BOP
V
C11
-------------
249V
35V
-------------- 7.1 = = = [Eq. 140]
T
Restart
RESTART[5:0] 40.96ms  25 40.96ms  1.024s = = = [Eq. 141]