An368 – Cirrus Logic AN368 User Manual
Page 34
AN368
34
AN368REV2
Component U2 is a positive edge D-type flip-flop and is used as a frequency divider. The output terminal Q is
connected to input D. The CLK signal acts as a clock signal, and the output Q changes on the positive edge
on the CLK signal. When Q is high, FET Q3 is turned ‘ON’, and the red LED string is shorted out. When Q is
low, FET Q3 is turned ‘OFF’, and charge is delivered to the red LED string.
Figure 15 shows the basic operation of the Synchronizer Circuit. The CLK signal is divided from the secondary
winding voltage of the transformer, V
sync
. The polarity of the secondary winding is determined so that the rising
edge of the inductor voltage triggers the output signal to change. Resistor R3 also determines the input current
applied to the CLK signal. A capacitor can be added to filter out the resonant ringing on the secondary winding
voltage.
Resistor R2 in conjunction with capacitor C16 act as a low-pass filter between input D and output Q. The
values of resistor R2 and capacitor C16 should be selected so that the propagation delay is large enough to
allow D to change sometime after the falling edge of the gate drive. This would ensure that any false clock
glitch will not propagate a toggle due to a changed D input. As the switching frequency decreases and the on-
time increases with lower light output, the values selected at full dim works for all ranges.
When a false clock glitch causes the Synchronizer Circuit to toggle, FET Q3 turns ‘ON’ when it should be ‘OFF’
or turns ‘OFF’ when it should be ‘ON’. As a result, the LED output current drops and current offset occurs
momentarily as the controller re-syncs to control the current.
The power supply section consists of diodes D6 and D10, voltage regulator diode D9, resistor R12, and
capacitor C10 of Figure 14. Voltage regulator diode D9 is ground referenced to the source of FET Q3. Two
main paths supply power to the circuit. The first path is from the secondary inductor voltage V
sync
. When
voltage V
sync
is positive, diode D6 will conduct, and the RMS current I
sync(rms)
will charge voltage regulator
diode D9. The second path is from the output voltage, where resistor R12 and diode D10 provide a path to
initially supply power to the CS1630 controller. In order to regulate the regulator diode voltage, the
recommended current I
D9
must be applied. Depending on the turns ratio of the secondary winding and the
main duty cycle of the converter, the first path may not provide enough current. In that case, resistor R3 should
be selected so that Equation 58 is satisfied.
The power consumption of resistor R36 should also be considered in designing the power supply section.
Figure 14 is a design example of the Synchronizer Circuit in a 120VAC, 9W flyback converter application
circuit with series load configuration.
Dual Gate
V
sync
V
L
GD
Figure 15. Waveforms of a Synchronizer Circuit
[Eq. 58]
I
D9
I
sync avg
V
MODEx
VCC
–
R
3
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+
=