Cirrus Logic AN368 - Manual (Page 25)

AN368
AN368REV2 25
The linearity of the second-stage current regulation is determined by the error between the expected currents
at any given dim level and the measured currents at that dim level. Percentage error I
error
at any particular dim
is given by Equation 50:
where,
I
calculate
= Current calculated in Equation 48 and 49
I
measure
= Current measured at dim level
If this error is zero across the operable system dim range, which may be from 2% to full brightness, the second
stage has ideal linear output current regulation. Note that this error definition does not include the errors due
to curve fitting the target color system. It is recommended to optimize the second stage first using this section
so that the remaining margin of error for the overall system output regulation is understood when the color
system is enabled.
b. Tune Flyback ZCD Fixed Delays for Optimum Valley-switching Performance
To minimize switching losses, the valley-switching performance needs to be optimized using the following
steps:
1. Probe the drain voltage of the second-stage FET so that the drain voltage resonant ringing can be
observed when the T2 time is over. Also probe the FBAUX pin on the IC. The two waveforms should be
similar, with the FBAUX voltage waveform being a phase-delayed and scaled-down version of the drain
voltage minus the DC boost output voltage V
BST
component (see Figure 5).
2. The internal ZCD comparator has a reference of 200 mV. If the ringing waveforms at the end of time T2
are greatly attenuated so that resonant voltage is barely above 200 mV, the device comparator will not
be able to detect the zero crossings on the signal applied to the FBAUX pin.
3. Automatic T
RES
probing:
i. For the IC to automatically measure the resonant frequency and use it for valley switching, enable
the PROBE bit within register Config7 at Address 39. Set the probe count PRCNT[3:0] bits in reg-
ister Config7 at Address 39 to obtain the desired probing frequency. It is recommended to leave this
setting at its max value initially. The automatic probing cycles can be viewed by setting the system
at a full dim level where it is always switching in CRM mode. The switching cycles that show more
than one valley are the T
RES
probe cycles. These should occur after every TT
N
number of switching
cycles, where TT
N
is proportional to the probe count PRCNT[3:0] bits.
ii. To disable resonant frequency probing and specify a fixed resonant period value, the PROBE bit
within the Config7 register can be disabled and the quarter resonant period can be set by steps of
100ns using the probe count PRCNT[3:0] bits in the Config7 register (see Equation 43).
4. Set bits CH1_ZCD[2:0] in register Config8 at Address 40 and bits CH2_ZCD[2:0] in register Config16
at Address 48 to ‘0’. These settings are used to account for the various path delays involved in between
the V
BST
crossing time at the drain voltage and the ZCD comparator tripping.
5. Set the system to full brightness so that it is in CRM mode. The valley-switching point for each channel
can be tweaked independently using bits CH1_ZCD[2:0] in the Config8 register and bits CH2_ZCD[2:0]
in the Config16 register.
6. Increment bits CH1_ZCD[2:0] in register Config8 by 1 LSB (50ns) and observe the valley-switching
point at the end of the channel 1 switching cycle on the FET drain voltage. Use the lowest delay time
setting that yields the desired valley-switching performance.
7. Configure bits RE1_ZCD[2:0] in register Config10 at Address 42 to the same value as bits
CH1_ZCD[2:0].
8. Repeat the steps above using bits CH2_ZCD[2:0] and bits RE2_ZCD[2:0] in register Config16 at
Address 48 for tweaking the valley-switching performance on channel 2.
I
error
I
calculate
I
measure
–
I
calculate
---------------------------------------------- 100  = [Eq. 50]