Cirrus Logic AN368 - Manual (Page 59)

AN368
AN368REV2 59
e. Minimum Measurable Peak Current
The minimum peak current level bits IPEAK[2:0] in register Config3 at Address 35 are set to ‘100’ and the offset
adjustment bits CLAMP[1:0] in register Config2 at Address 34 are set to ‘01’. Voltage V
IPK(min)
is calculated
using Equation 41.
f. T2 Time-out Configuration
The T2 time-out limit is configurable through the TIMEOUT[1:0] bits in register Config12 at Address 44. Bits
TIMEOUT[1:0] are configured to ‘00’ setting the T2 time-out limit to 45ms.
g. Automated Resonant Period Measurements
Bit PROBE is set to ‘1’ in register Config7 at Address 39, enabling automated resonant period measurements.
Set bits PRCNT[3:0] in register Config7 at Address 39 to ‘1111’. The number of switching cycles TT
Cycles
in
channel 1 between resonant period measurements is set using Equation 42:
This forces a resonant period measurement every 255 switching cycles.
Design Tip - Different second-stage output current settling points
Symptoms:
The final settled output current on both channels varies by a few milliamps (1mA to
2mA) between system power-ups at full dim. The difference between the two
distinct settling points generally decreases with dim (to approximately 50% or lower
dim levels).
Cause: The most likely cause of this problem is that the resonant frequency is different
between the two channels by more than about 100ns. As the CS1630 controller
generally probes on the same channel to extract the resonant period when
automatic T
RES
probing is switched on, depending on the number of re-syncing
events that occur on startup and the final channel on which the controller ends up
probing to obtain T
RES
, the output current settling point will be different.
Solution: One solution is to disable automatic T
RES
probing clearing bit PROBE and setting
T
RES
to a fixed value by setting the PRCNT[3:0] bits within register Config7. This
has the disadvantage that if the resonant frequency differs by a lot due to board-to-
board or component-to-component variations, then the fixed value will not be
accurate. Determine the reason for the mismatch of the resonant period on the two
channels.
Design Tip - Deep DCM events at less than full dim levels
S ymptoms: A current probe is attached to the system output to observe the channel output
current I
CHx
. The output current on one of the channels wobbles a little at a periodic
rate and the wobble does not extend for more than a switching cycle.
Cause: The cause for this is a bug in the controller logic that causes the TT to extend by
an unusually large amount during T
RES
probe cycles.
Solution: This issue is mostly benign and does not sacrifice performance. However, to
reduce the frequency of or completely remove these wobbles, two things can be
done:
1. The automatic T
RES
probing frequency can be reduced to the minimum value by setting
the PRCNT[3:0] bits within Config7 register to ‘1111’.
[Eq. 123]
V
IPK min  
1.4 V
IPEAK[2:0] 1 +   16    15 +   CLAMP[1:0] 8     – 8  +
512
---------------------------------------------------------------------------------------------------------------------------------------------------
 
 
 =
1.4 V =
4 1 +   16    15 +   1 8     – 8  +
512
-----------------------------------------------------------------------------------------
 
 

0.216V =
TT
Cycles
16 P  RCNT[3:0]   15 + 16 15    15 + 255 = = = [Eq. 124]