Cirrus Logic AN368 - Manual (Page 51)

AN368
AN368REV2 51
Step 18) Layout
Basics for any power layout are as follows:
• Keep power traces as short as possible.
• Keep the controller away from power components and traces if possible. Keep sensitive traces (all sense
inputs) away from high dv/dt traces such as FET drain, FET gate drive, and auxiliary windings.
• Isolate control GND from power GND.
- All control components must be grounded to SGND.
- A single thick trace must connect SGND to GND and then extended to the flyback current sense
resistor R21 with a short run.
- The connection between the boost output capacitor C6 and resistor R21 must be short.
• Decouple the capacitor directly at the VDD pin of the CS1630 to SGND.
• Run sense traces, especially current sense, away from power-carrying traces characterized by high dv/dt
(fast rise/fall times) traces such as collectors and drains of transistors Q1, Q2, and Q5 or the auxiliary
windings or the SOURCE pin.
• Further details are available in application note AN346 CS150x and CS160x PCB Layout Guidelines.