Cirrus Logic AN368 - Manual (Page 41)

AN368
AN368REV2 41
Step 14) Boost Zero-current Detection
The CS1630 uses zero-current detection (ZCD) to minimize switching losses. The ZCD algorithm is designed
to turn ‘ON’ the FET when the resonant voltage across the FET is at a low point. Valley switching reduces the
CV
2
power losses associated with rerouting charge from the body capacitance of the FET. Similar approaches
are taken when turning ‘ON’ the boost FET Q1 and the flyback FET Q5. Pin BSTAUX is designed to monitor
the resonant voltage from the auxiliary winding of the boost inductor L3. The boost ZCD functions exactly in
the same manner as the flyback ZCD.
The auxiliary winding of the boost inductor L3 is also used to drive the charge pump circuit to develop the
supply voltage, V
DD
. It is recommended to use the boost auxiliary winding for the boost ZCD. The auxiliary
winding turns ratio must be designed to develop ~22V peak-to-peak under nominal conditions.
The boost inductor auxiliary winding turns ratio is determined at the boost overvoltage threshold V
BOP(th)
. The
maximum voltage V
C11
across capacitor C11 should be less than 35V. Assuming 1V tolerance, the minimum
turns ratio for the boost inductor auxiliary winding is calculated using Equation 67:
For optimum efficiency, Voltage V
C11
should be as low as possible to minimize losses on FET Q4. For dimmer
compatibility at low conduction angles, this voltage is the only source of charge reservoir that feeds the
controller with voltage V
DD
and hence should be as high possible. To comply with the largest range of dimmers
at their lowest conduction angles, it is recommended to have the maximum permissible voltage across
capacitor C11. The pin BSTAUX current must be limited to less than 1mA. A series resistor of at least 22k

must be used to limit the current.
Step 15) Enable and Tune Protection Mechanisms
a. Protection Restart
Second-stage protection mechanisms—OCP, OLP, OVP, and VDIFF—are configured by default to unlatched
faults. Unlatched protection events shut down the power conversion for a defined period, and then the event
attempts a system restart. The speed at which to perform the restart and the time duration of the restart are
configurable by programming bit FAULT_SLOW and bits RESTART[5:0], respectively.
Bit FAULT_SLOW in register Config51 at Address 83 sets the restart countdown timer. By default, slow restart
is disabled and the countdown timer is set to 25.6
s. If bit FAULT_SLOW is set to a ‘1’, slow restart is enabled,
and the countdown timer is set to 40.96ms.
Bits RESTART[5:0] in register Config51 at Address 83 configure the restart time and are dependent on bit
FAULT_SLOW. If slow restart FAULT_SLOW is enabled, then
where,
T
Restart
varies from 0 to 2.58s in 40.96ms steps
If FAULT_SLOW is enabled, then
where,
T
Restart
varies from 0 to 1.6ms in 25.6 s steps
The recommended setting for time T
Restart
is 1s.
The four second-stage protection mechanisms can be configured to shut down only the second stage or the
boost stage plus the second stage. The FAULT_SHDN bit in register Config51 at Address 83 configures the
behavior for the event shutdown. By default, bit FAULT_SHDN is ‘0’ and disables the second stage only when
a protection event occurs. Setting bit FAULT_SHDN to a ‘1’ disables the second stage and the boost stage in
a fault state.
N
L3
N
BSTAUX
----------------------
V
BOP th  
V
C11
--------------------- = [Eq. 67]
T
Restart
RESTART[5:0] 40.96ms  = [Eq. 68]
T
Restart
RESTART[5:0] 25.6 s  = [Eq. 69]