Cirrus Logic AN368 - Manual (Page 32)

AN368
32 AN368REV2
3. Disable the color system and boost stage by forcing gains GAIN
DR
and GAIN
DTR
to a value of 1 and the
converter to a flyback-only stage. This can be done by the following commands:
i.
Write 0x40 to Address 210 (forces the color gain for channel 1 in 2.8 unsigned format).
ii. Write 0x40 to Address 211(forces the color gain for channel 2 in 2.8 unsigned format).
iii. Write 0x04 to Address 212 (sets the bit that forces the above gain values onto the channel 1 and
channel 2 color gains to the second-stage control loop in the IC).
iv. Write 0xC0 to Address 231 (disables boost stage and enables the flyback-only stage).
4. Enabling the ability to force the dim value to a desired value by writing 0x01 to Address 237. The 8-bit
MSB of the 12-bit dim value can be forced by writing to the control register at Address 238. A value of
0xFF corresponds to 100% of the output current, a value of 0x7F corresponds to 50%, a value of 0x3F
corresponds to 25%, and so on. Force the dim to the desired value by writing the appropriate value to
Address 238.
5. Apply 200VDC for a CS1630-based system, and 400VDC for a CS1631-based system.
6. Measure the output currents on the two channels.
7. Turn ‘OFF’ the DC source.
8. Repeat step 5 to step 7 across various dim values and measure regulation. The values obtained provide
the most accurate information about the flyback output regulation accuracy.
Step 6) Synchronizer Circuit Design
The CS1630 controller provides support for phase synchronization to ensure that the voltage requirements of
the dual-channel topology are satisfied. Since the controller has no method to sample the output voltages on
the two channels, a calculation based on the measured T1 and T2 duration is used to estimate the output
voltage levels. If the calculation indicates the voltage level on channel 2 has exceeded channel 1, an exception
is indicated and counted. If the number of exceptions exceeds a programmable threshold, a synchronization
event occurs, which indicates back-to-back channel 1 slots are executed by the controller. This document first
explains the operation of the Synchronizer Circuit and then describes the design process.
a. Phase Synchronization
The programmable threshold for the synchronization is programmed through the EXIT_PH[3:0] and
DECL_PH[3:0] bits in register Config15 at Address 47. Bits EXIT_PH[3:0] configure the minimum number of
switching cycles between synchronization events, and bits DECL_PH[3:0] configure the number of exceptions
before declaring a re-synchronization event. Phase synchronization is enabled by asserting the RESYNC bit
in register Config17 at Address 49.