Cirrus Logic AN368 - Manual (Page 31)

AN368
AN368REV2 31
f. Procedure for Measuring the Second-stage Output Current Regulation
This step describes the procedure for measuring the second-stage output current on both channels across the
operable dim range of the system. Once this data is available, the error can be characterized in the second-
stage current regulation, as described in the previous section.
1. Connect to the LED driver board using the CS1630 I 2 C communication port.
2. Enter test mode by writing 0x73 to Address 249 after entering control port mode. This allows the
designer to read the internal 12-bit dim level as perceived by the chip.
3. Disable the color system by forcing the gains, GAIN
DR
and GAIN
DTR
, into the second stage to 1. This
can be done by the following commands:
i.
Write 0x40 to Address 210 (forces the color gain for channel 1 in 2.8 unsigned format).
ii. Write 0x40 to Address 211 (forces the color gain for channel 2 in 2.8 unsigned format).
iii. Write 0x04 to Address 212 (sets the bit that forces the above gain values onto the channel 1 and
channel 2 color gains to the second-stage control loop in the IC).
4. Set the conduction angle to 180

using an AC source, such as Chroma 61502.
5. Turn on the AC source, and allow the system and output currents and the internal boost and second-
stage control loops to settle by waiting 1 to 2 minutes.
6. Measure the output currents on the two channels. This is the full-scale output current ICH1_fullscale
and ICH2_fullscale, as described in the previous section. Then the conduction angle of the AC source
can be swept, and the output currents at different conduction angles can be measured, as described in
steps 7 through 12.
7. Set the conduction angle to the desired value using an AC source, such as Chroma 61502.
8. Turn on the AC source and allow the system and output currents and the internal boost and second-
stage control loops to settle by waiting 1 to 2 minutes.
9. Read the internal 12-bit dim level of the system by first writing to Address 245 to allow the chip to capture
the internal 12-bit dim and then read Addresses 244 and 245. The top 8 MSBs of the 12-bit dim level
are given by the value read from Address 244 and the lower 4 LSBs are given by the top 4 MSBs of the
value read from Address 245.
10. Measure the output currents on the two channels. This is output current that the second-stage control
loop regulates when given the dim value recorded in step 9.
11. Calculate the current error on both channels, as described in previous section.
12. Repeat steps 7 to 11 for different conduction angles across the operable dim range. Ensure that there
is enough uniformly spaced data points for seeing the dim-versus-current and dim-versus-error profiles.
Note that in some systems due to noise in the layout when the system is at full or close to full power, the noise
on the LED driver may prevent communication with the IC. In such designs the method described above for
checking the output current regulation may not work. Moreover, trying to communicate with the IC might reset
the I
2 C interface, putting the IC out of test mode and leading to reading out incorrect values and disrupting the
process because the color system might no longer be disabled due to the reset. It is recommended to read
Address 249 and ensure that it is still set to 0x73 (the value that was set in step 2) and that the IC is still in test
mode after every communication failure, if there is one. If the IC is no longer in test mode, then it is advised to
power cycle the chip (which includes removing and re-attaching the VDD supply signal from the programmer
box) and starting from step 1 again to collect the remaining dim data points.
In case the IC is not responsive when the system is alive to read out the internal dim level, a different approach
might have to be used to perform the above procedure, which involves forcing the second-stage dim level.
1. Connect to the LED driver board using the CS1630 I 2 C communication port.
2. Enter test mode by writing 0x73 to Address 249 after entering control port mode. This allows the
designer to read the internal 12-bit dim level as perceived by the chip.