Cirrus Logic AN368 - Manual (Page 35)

AN368
AN368REV2 35
c. Synchronizer Circuit RC Filter Design
The Synchronizer Circuit has an RC filter in the feedback path from Q to D. This circuit should be tuned for
optimum synchronizer performance in the event of noise events on the clock at low dim angles (see Figure 16).
The noise events are design dependent and should be reviewed when major changes occur in the secondary
power train (that is, the inductor or transistor). In order to choose the correct RC filter, which can make the
Synchronizer Circuit non-responsive to the noise glitch, the timing constraints illustrated in Figure 16 must be
met.
Resistor R2 and capacitor C16 form an RC filter used to suppress noise on the flip-flop U2 clock pin. The noise
on the clock pin can be injected due to various noise sources, for example noise on the flip-flop input signal,
VCC jitter, and common mode noise. Distortion on the clock signal causes false toggling of the flip-flop, as
shown in Figure 16. In the absence of a filter, erroneous output current regulation that leads to color shifts and
color flicker could occur during operation behind a dimmer.
Step 7) Color System Parameters
This step details the implementation of the CS1630/31 color control block, which calculates the gains for each
channel of the flyback every half line-cycle based on the dim and temperature values. The CS1630/31 is a
two-string LED driver and is designed to change the color temperature of the light output by independently
varying the gains of the two LED strings (of different colors) to achieve varying levels of color mixing. This
feature can be used to make the color temperature versus dim characteristics of the light similar to that of an
incandescent light bulb.
The color system may place additional constraints on the minimum desired lumen output, which corresponds
to a minimum output current and a minimum dim setting. The minimum dim setting for the second stage is
configured using register S2DIM at Address 37. Enforced minimum dim percentage dim
min
is determined by
Equation 59:
GDRV
CLK
T1
TT
Noise Delay § 150 ns to 180 ns
Figure 16. Noise Glitch on the CLK Input of Synchronizer Flop
[Eq. 59] dim
min
S2DIM[7:0] 16 15 + 
4095
--------------------------------------------------------
 
  100 
=